Advertisement
RXD-DV9
QQ
3 7 63 1515 0
Pin No.
Pin Name
83
CP1
84
MIRRI
85
EQVCC
86
RFEQ0
87
BCATH
88
EQIN
89
RFAGCO
90
AGCC
91
AGCI
92
EQGND
93
AGCLEVEL
94
AGCB
95
AGCP
96
RDPF
97
EQG
98
EQF
99
PLLF
100
VZOCTL
3. Pin descrption of data processor DIC1(KS1453)
Pin No.
Pin Name
1
D GND
2
DPS CS
3
HAD
4
D GND
TE
5~12
HAD7~HAD0
L 13942296513
13
DVDD
14
CLK27D
15
XTO1
16
D GND
17
DD15
18
DD0
19
DD14
20
DD1
21
D GND
22
DD13
23
DD2
24
DD12
25
DD3
26
DVDD
27
DD11
28
DD4
29
DD10
30
DD5
31
D GND
32~35
DD9~DD7
36
D GND
37
ZLCAS
38
ZUCAS
39
ZWE1
www
40
ZWE0
41
ZOE1
42
DVDD
43
ZOE
44
ZRAS
45,46
DADR8,DADR7
47
D GND
8
CIRCUIT DESCRIPTION
I/O
-
RC connection terminal of RC value of peak hold, for RFRP generation.
I
Input terminal for MIRR signal generation.
-
Power voltage input signal for RF EQ.
O
RF EQ output terminal.
I
BCA comparating level control terminal.
I
RFAGCO input terminal for RF EQ.
O
RF AGC AMP output terminal.
-
CAP connection terminal for time constant of AGC.
I
AGC voltage input terminal while in AGC hold.
-
Power ground input terminal for RF EQ.
I
AGC level control voltage input terminal(3.5V) while in AGC hold off.
-
RC connection terminal for RC value of bottom hold, for RF AGC.
-
RC connection terminal for RC value of peak hold, for RF AGC.
-
Bias resistance connection terminal for selecting RF EQ frequency.
I
RF EQ boost gain control voltage input terminal.
I
RF EQ peak frequency control voltage input terminal.
I
Wide-band PLL compatible RF EQ peak frequency control terminal.
I
RF EQ zero control terminal.
I/O
-
Digital ground.
I
Chip select(active low).
I
Micom resistor select (L resistor data).
-
Digital ground.
I/O Micom data bus.
-
Digital power(+5.0V).
I
System clock input for 26.16MHz.
O
System clock output for 26.16MHz.
-
Digital ground.
I/O DRAM data bus.
I/O DRAM data bus.
I/O DRAM data bus.
I/O DRAM data bus.
-
Digital ground.
I/O DRAM data bus.
I/O DRAM data bus.
I/O DRAM data bus.
I/O DRAM data bus.
-
Digital power(+5.0V).
I/O Digital data bus.
I/O Digital data bus.
I/O Digital data bus.
I/O Digital data bus.
-
Digital ground.
I/O DRAM data bus.
-
Digital ground.
O
DRAM low column address strobe.
O
DRAM upper column address strobe.
O
DRAM write enable 1(8M only).
O
DRAM write enable 0(4M,8M,16M ).
O
DRAM output enable 1(16M mode DADR9 ).
x
ao
y
-
Digital power(+5.0V).
O
DRAM output enable 0.
.
i
O
DRAM low address strobe.
O
DRAM address bus.
-
Digital ground.
8
Description
Description
Q Q
3
6 7
1 3
u163
.
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
Hide quick links:
Advertisement
