Block Diagram - Denon POA-3012CI Service Manual

M3062LFGPGP (IC701)
QQ
3 7 63 1515 0
P1
2
P1
P1
P0 /AN
7 07
P0 /AN
6 06
P0 /AN
5 05
P0 /AN
4 04
P0 /AN
3 03
P0 /AN
2 02
P0 /AN
1 01
P0 /AN
0 00
P10 /AN
7 7
P10 /AN
6 6
P10 /AN
5 5
P10 /AN
4
P10 /AN
3
P10 /AN
2
P10 /AN
1
AV
P10 /AN
0
V
AVcc
P9 /AD /S
7 TRG
P9 /ANEX1/S
6 OUT
P9 /ANEX0/CLK4
5
TE
L 13942296513

BLOCK DIAGRAM

Port P0
Internal peripheral functions
www
Port P11
.
8
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75 74 73 72 71 70 69 68 67
/D
76
10
/D 77
1 9
/D 78
0 8
79
/D
7
/D 80
6
/D 81
5
/D 82
4
/D 83
3
/D
84
2
/D
85
1
/D
0 86
M16C/62P Group
/KI
87
3
/KI
88
2
/KI
89
1
KI 90
4/ 0
91
3
92
2
93
1
94
SS
95
0
96
REF
97
98
4
IN
99
4
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
8 8
8
Port P1 Port P2
<V ports>
CC2
A-D converter
(10 bits
Timer (16-bit)
Expandable up to 26 channels)
Output (timer A): 5
Input (timer B): 6
clock synchronous serial I/O
Three-phase motor (8 bits
control circuit
CRC arithmetic circuit (CCITT )
(Polynomial : X
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
<V ports> <V
CC1
x ao
Port P14 Port P12 y
(Note 3) (Note 3) (Note 3)
i
2
8
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8
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
Q Q
3 6 7 1 3
8
8
8
Port P3 Port P4 Port P5
System clock generator
8 channels
X
X
X
CIN
PLL frequency synthesizer
UART or
Ring oscillator
3 channels) Clock synchronous serial I/O
X
(8 bits
16 12 5
+X +X +1)
R0L
SB
R1L
USP
R2
ISP
R3
INTB
A0
PC
A1
FLG
FB
ports>
CC2
u163
Port P13
(Note 3)
.
Note 1: ROM size depends on microcomputer type.
8
Note 2: RAM size depends on microcomputer type.
Note 3: Ports P11 to P14 exist only in 128-pin version.
21
POA-3012CI
2 9 9 4 2 8
51
50
P4 /A
2 18
49
P4 /A
3 19
48
P4 /CS0
4
47
P4 /CS1
5
46
P4 /CS2
6
45
P4 /CS3
7
44
P5 /WRL/WR
0
43
P5 /WRH/BHE
1
42 P5 /RD
2
41 P5 /BCLK
3
40 P5 /HLDA
4
P5 /HOLD
39
5
P5 /ALE
38
6
37 P5 /RDY/CLK
7 OUT
36 P6 /CTS /RTS
0 0 0
P6 /CLK
35
1 0
P6 /RxD /SCL
34
2 0 0
P6 /T D /SDA
33
3 X 0 0
32 P6 /CTS /RTS /CTS /CLKS
4 1 1 0
P6 /CLK
31
5 1
30 P6 /RxD /SCL
6 1 1
29 P6 /T D /SDA
7 X 1 1
28 P7 /T D /SDA /TA0
0 X 2 2 OUT
27
P7 /RxD /SCL /TA0 /TB5
1 2 2 IN
26
P7 /CLK /TA1 /V
2 2 OUT
1 5 0 5 8 2 9 9 4
8
Port P6
<V ports>
CC1
-X
IN OUT
-X
COUT
2 channels)
X
Memory
ROM
(Note 1)
RAM
(Note 2)
Multiplier
m
co
9 9
1
(Note)
(Note)
IN
2 8 9 9