Sony HMD-A400 Service Manual page 28

a a , b a b b b , c c c , d c d , e d d e e e , f f f f ) Board
a b c d e f
(3) Schematic Diagrams of D (a
3
1 2
D
-a
A
( µ-COM, DEFLECTION CONTROL)
ad1
B
C902 2.2
R902 1k
C903 2.2
R903 1k
C C904 2.2
R904 100
C905 2.2
R905 1k
R914
R948
1.4k 33.2 R906 1k
H-DRIVER
C906
R915
30.1k 2.2
1N4148
ac1
R949
10k
ABL/O
R950 C924
16k 4.7
D MENU
C909
D911
470p
1N4148
CN904
3P
FB902 0.45µH
USB DM 1
USB DP 2
FB903 0.45µH
GND
3
+5V C912 C913
TO D-f BOARD
22p 22p
P7000
R921
1k
CN903
E
4P
C930 R943
MENU
220p 1k
MENU 1
ORANGE/LED
ORANGE/LED 2
GREEN/LED
GREEN/LED 3 VSYNC/O
GND
4
HSYNC/O
TO H BOARD
P701
Q902
H2N3904
H SYNC BUFF
C915
100p
D901
R919 0.5 HZ5C1
F
4.7k
CN902 R920
10k
7P
H-IN 1
D902
GND 2 MTZJ5.1A
V-IN
3
PCDET 4
R952 47
SDA 5
SCL 6
R947 47
PC+5V(NC) 7
C926 C927
TO A BOARD
100p 100p
G
CN305
CN901
10P
SCL/I 1
SDA/I
2
CLAMP 3
GND 4
G1 5
V_RTN 6
H_RTN 7
GND 8
H
SOG 9
Auto-Size(NC)
10
TO A BOARD
CN302
I • Divided circuit diagram
One sheet of D board circuit diagram is divided into six
sheets, each having the code D-a to D-f. For example, the
destination ab1 on the D-a sheet is connected to ab1 on the
D-b sheet.
a b 1
Ref. No.
Circuit diagram division code
4
5 6
+5V
R900
2.7k
IC901
ST72754
CPU +5V
TH602
C900
10k
0.1
PC0/
PA0/OCMP
HSYNCDIV
R907 R942
IC903
47
1k R940
M51951B
10k
PC1/VA TEST/Vpp RESET
5.0
5.0
PC2/PWM2 Reset 3 1
OUT IN
GND
1.2
2.0 2
C923
PC3/PWM3 PA1/RDI 2.2
R941
R953
1
47
10k
PC4/PWM4 PA2/TDO
R954
0 4.7k
R955
PS5/PWM5 PA3
10k
4.9
PS6/PWM6 PA4
2.5 2
4.9
PC7/PWM7 PA5
+5V
D910 0.1
PB7/AIN3/
PA6
PWM1
R908 10k 3.1
R936 X901 C922
2.2 1M 24MHz 22p 50V
R909 1k
PB6/AIN2/
OSCIN
PWM0
C928
C921
0.1 5
22p 50V
R911 1k 2.3 R937 0
PB5/AIN1 OSCOUT
R912 10k C925
0.1
0.1
PA7/
PB4/AIN0
BLANKOUT
4.9
FB901 2µH 4.9
VDD PB3/SDAI
C908
0.1
5.0
USBVCC PB2/SCU
+5V
0.7-4.0
USBDM PB1/SDAD
D908
R935
10k 1SS119
4.1
USBDP PB0/SCLD
C911 C910 C907
R946
0.1 0.1 10 5.0 100
VSS PD6/CLAMPOUT D907
1N4148
0.5 R913 +5V
3
1.7 1k
HSYNCI PD5/HFBACK
R951
R926
4.2 4
100 4.7k
0.2
VSYNCI PD4/ITB
R925
0
-0.6 10k
PD0/ PD3/ITA/
VSYNCO VFBACK
0.4
4.6
PD1/ PD2/
H_RETURN
HSYNCO CSYNCI
D906 D905
HZ5C1 HZ5C1
+5V
R918
10k
C914
R944
100p
470
Audio_Mute
+5V
R928 R929 R930
10k 10k 10k
R931
10k
D903 D904
HZ5C1
HZ5C1
+5V
R924
1k
4.6
Q901
H2N3904
0.2 C SYNC BUFF
R922 R923
10k 10k
• D - a BOARD WAVEFORMS
1 2
3.4 Vp-p (H)
3.2 Vp-p (H)
Schematic diagram
5-15
D
-a board
7 8 9
R402 C406
2.1k 3300p
1% 100V
+12V
C570
R5121
10K 10
50V
0.7
2
C563
7
330 + 6
16V
0.7
Q541
2SD667 C409 1
- 4
1000p
R5122 TILT DRIVE
100V
47k IC401
-2.0 TDA8172
-1.4
V OUT
IC504(1/2)
LM358
0.3
R5124
AMP
2 8 100
C580
1
0.1
3
100V
4 -2.0
0.3
Q542
2SB647
C571 R5123
0.1 10k TILT DRIVE
-12V
50V
C572
47
16V
C579
C581
3300p R5125
430 0.22 50V
100V
R5120
46.4k -12V
Q526
RN1203 R529
BUFF
1k
0.8
0.1
0.2 0.8
HUNLOCK CLBL
+5V
5.0 0.4
SCL HSYNC
R934 6
4.9 0
C920
47
0.1
SDA VSYNC
7 2.9
IC902
24LC16 COR VOUT1
EEPROM
8 2.9
VSOMD VOUT2
Vcc A0 C502
0.1
3.2 9 2.8
4.9 100V
VAGC EWDRV
TEST A1 C510 C534
R502
3.1 1000 0.1
22.1k 1%
16V 50V
VREF VCC
SCL A2
2.7
5.0
VCAP DGND
SDA Vss
C503
0.1 5.7
4.9
100V
GNDS HDRV
C504 0.01 100V
10
R932
R503 4.7k
22
HPLL1 PGND
C505
2.4
R933 0.1
22
HBUF BDRV
R505
R504
2.8k
1.0 5.3 R592
1% 732
47k
1%
HREF BIN
C919 C918
C506
47p 47p
0.01 2.6 2.5
100V
HCAP BSENS
C507 R507
4700p 4.5 1.5 10k
100V
HPLL2 BOP
C531
0.022
5.4 2.5
100V
HSMOD XRAY
6.1
FOCUS HFLB
6.3 0.2
IC501
R501
TDA4841 27k
DEFLECTION
CONTROL
4 5
3
2.8 Vp-p (24MHz)
5.0 Vp-p (H) 4.0 Vp-p (V)
l l l l l
10 11
12 13
ad2
ab1
+15V
D402 R403
1N4002
1 1/2W
C404
1000
C408 25V
470
35V
-14.3
ab2
ab3
3
5
0.1
R407 C405
330 0.22
R401 1W 50V
2.15k
C403
0.022
100V
R404 R406
0.75 1.5
2W
C402
470
25V
CN505 2P
1 ROTATION+
2 ROTATION-
TILT(ROTATION)
COIL
ae1
R411 R412
6.8k 6.8k
1% 1%
BLANK OUT
R510 R511
100 100
C512 C513
220p 220p
50V 50V
+12V
L509
150µH
R571
4.7k
R508 R522
13k 4.7k
R513
100
HDRV
R500
43
BDRV
BOP
C509
3300p
100V
R596
95.3k
HFLB
D501
R506 C508
1SS119
10k 100p
50V
FOCUS
MUTE
HUNLOCK
G1/VBLK
ab4
B-SS3578<U/C>-D..-P1-EPS05
6 7 8
5.0 Vp-p (H) 5.0 Vp-p (V) 3.0 Vp-p (V)
5-16
14
9 0
2.0 Vp-p (V) 12.0 Vp-p (H)