Onkyo HT-R540 Service Manual page 82

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-27
Q2002 : AK4384 (192kHz 24-Bit 2ch DAC)
BLOCK DIAGRAM
P/S
SM UTE/CSN
µP
ACKS/CCLK
Interface
DIF0/CDTI
LRCK
Audio
Data
BICK
Interface
SDTI
PDN
TERMINAL DESCRIPTION
No. Pin Name
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 SMUTE/
CSN
7 ACKS/
CCLK
8 DIF0/
CDTI
9 P/S
10 AOUTR
11 AOUTL
12 VCOM
13 VSS
14 VDD
15 DZFR
16 DZFL
MCLK
Clock
De-emphasis
Control Divider
8X
ATT
Modulator
Interpolator
8X
ATT
Interpolator Modulator
I/O Function
Master Clock Input Pin
I
An external TTL clock should be input on this pin.
I Audio Serial Data Clock Pin
I Audio Serial Data Input Pin
I L/R Clock Pin
Power-Down Mode Pin
I
When at "L", the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
I Soft Mute Pin in parallel mode
"H": Enable, "L": Disable
Chip Select Pin in serial mode
I
I
Auto Setting Mode Pin in parallel mode
"L": Manual Setting Mode, "H": Auto Setting Mode
Control Data Clock Pin in serial mode
I
I Audio Data Interface Format Pin in parallel mode
Control Data Input Pin in serial mode
I
I
Parallel/Serial Select Pin
"L": Serial control mode, "H": Parallel control mode
O Rch Analog Output Pin
O Lch Analog Output Pin
O
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1mF ceramic capacitor in parallel with
a 10mF electrolytic cap.
- Ground Pin
- Power Supply Pin
O Rch Data Zero Input Detect Pin
O Lch Data Zero Input Detect Pin
PIN CONFIGURATION
VDD
MCLK
VSS
VCOM
BICK
SDTI
DZFL
DZFR
LRCK
SCF
PDN
AOUTL
LPF
SMUTE/CSN
SCF
ACKS/CCLK
AOUTR
LPF
DIF0/CDTI
(Internal pull-up pin)
TX-SR504/504E/8450
DZFL
1 16
DZFR
2 15
3 14 VDD
4 13 VSS
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View
5 12
VCOM
6 11 AOUTL
7 10 AOUTR
P/S
8 9