LG U8110 Service Manual page 21

3. TECHNICAL BRIEF
A. Block Diagram
Figure. Simplified Block Diagram
B. CPU Hardware Subsystem
The CPU subsystem incorporates:
• CPU Sub chip
• Backplane
• JTAG
• DMA Controller
• System Buffer RAM
• Boot ROM
• External Memory Interface (EMIF) for connection to external SRAM and Flash memories.
The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speed
Bus) and APB (Advanced Peripheral Bus) for the peripheral buses.
There are two AHB busses, the CPU AHB and the DMA AHB.
Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking.
The reset lines are all asynchronously asserted low and synchronously negated high.
The CPU subsystem has separate clocking and reset for the ARM946, AHB system, EMIF and DMAC.
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