Kenwood KVT-627DVDY Service Manual page 23

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MICROCOMPUTER'S TERMINAL DESCRIPTION
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Disc Controller Microcomputer: MN103S71F (X37: IC4)
Pin No. Pin Name
1 SW_2
2 SW_3
3 CDON
4 VDD3
5 VSS
6 FG
7 SW_4
8,9 FADR17,18
10 FADR11
11 FADR9
12 VDD15
13 FADR8
14,15 FADR13,14
16 NWE
17,18 FADR16,15
19 DRAMVDD15
TE
20 DRAMVSS
L 13942296513
21 VSS
22 FADR12
23~30 FADR7~0
31 VSS
32 VDD3
33~40 FDT0~7
41 NCE
42 FADR10
43 NOE
44 MMOD
45 NRST
46 VSS
47 SCLOCK
48 SDATA
49 TxD/EXTRG0 I/O
50 RxD/EXTRG1 I/O
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51 VDD3
52 OSCI
.
53 OSCO
54 VSS
I/O Application
I 8cm Ej-STOP, Lo-START detection
I Lo-START detection
O CD-LD ON
- VDD (3.3V)
- VSS
I Motor FG input
I Lo-END detection
O Address output to FLASH
O Address output to FLASH
O Address output to FLASH
- VDD (1.5V)
O Address output to FLASH
O Address output to FLASH
O Right signal output to FLASH
O Address output to FLASH
- DRAM power supply (1.5V)
- VSS for DRAM
- VSS
O Address output to FLASH
O Address output to FLASH
- VSS
- VDD (3.3V)
I/O Data input/output with FLASH
O Chip select signal output to FLASH
O Address output to FLASH
O Read signal output to FLASH
I Test mode switching signal
I Reset input
- VSS
I/O Dwire clock terminal
I/O Dwire data terminal
Serial transmission/
Dwire trigger terminal
Serial reception/
Dwire trigger terminal
- VDD (3.3V)
x ao u163
y
I Oscillation input (16.897849MHz)
i
O Oscillation output (16.897849MHz)
- VSS
2 9
8
Pin No. Pin Name
55 OFS_TE
56 DRV1
57 DRV2
58 DVDON
59 STEP_A
60 STEP_B
61 Lo/Ej
62 LO.MUTE
63 VSS
64 DRV.MUTE
65 BMS
66 LIM-SW
67 Gain_SW
68 FEPCK
69 FEPDT
70 FEPEN
Q Q
71 DRAMVSS
3 6 7 1 3 1 5
72 DRAMVDD15
73 DRAMVDD33
74 VDD3
75 FG
76 TX
77 VDD15
78 VSS
79 TSTSG
80 VFOSHORT
81 JLINE
82 BDO
83 OFTR
84 AVSSD
85 ROUT
86 LOUT
87 AVDDD
88 VCOF
89 TRCRS
90 AVDDC
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91 WBLIN
.
92 CSLFLT
93 RFDIF
KVT-627DVD/627DVDY/717DVD
KVT-737DVD/747DVD/767DVD
9 4 2 8
I/O Application
O CD TE offset cancel output
O Drive output for spindle drive
O Focus balance adjustment output
O DVD-LD ON
O Thread control output A
O Thread control output B
O Lo/Ej control terminal
O Lo/Ej mute terminal
- VSS
O Driver mute control
O Spindle short brake control
I LIM-SW detection
O PDIC Gain switching
O FEP clock output
O FEP data output
O FEP enable signal
- VSS for DRAM
0 5 8 2 9 9 4 2 8
- DRAM power supply (1.5V)
- DRAM power supply (3.3V)
- VDD (3.3V)
I Motor FG input
O Output for digital OUT
- VDD (1.5V)
- VSS
O EQ calibration signal
O Not used.
O J-line setting output
I Dropout signal input
I Off-track signal input
- VSS for analog
O MASH Rch audio output
O MASH Lch audio output
- VDD (3.3V) for analog
I JFVCO control voltage
m
I Track loss generation signal input
- VDD (3.3V) for analog
I WBL input
I Not used
I Not used
9 9
9 9
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