Yamaha Portatone PSR 1000 Service Manual page 19

AD1854JRSRL (XY782A00) DAC (Digital to Analog Converter)
PIN
NAME I/O
NO.
1 DGND I Digital Ground
2 MCLK I Master Clock Input. Connect to an external
clock source at either 256, 384 or 512 Fs.
3 CLATCH I Latch input for control data. This input is
rising-edge sensitive.
4 CCLK I Control clock input for control data. Control
input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.
5 CDATA I Serial control input, MSB first, containing 16 bits
of unsigned data per channel. Used for specifying
channel-specific attenuation and mute.
6 384//256 I Selects the master clock mode as either 384
times the intended sample frequency (HI) or
256 times the intended sample frequency (LO).
The state of this input should be hardwired to
logic HI or logic LO, or may be changed while
the AD1854 is in power-down/reset. It must not
be changed while the AD1854 is operational.
7 X2MCLK I Selects internal clock doubler (LO) or
internal clock = MCLK (HI).
8 ZEROR O Right Channel Zero Flag Output. This pin
goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
9 DEEMP I De-Emphasis. Digital de-emphasis is
enabled when this input signal is HI. This is
used to impose a 50 µs/15 µs response
characteristic on the output audio spectrum
at an assumed 44.1 kHz sample rate.
10 96//48 I Selects 48 kHz (LO) or 96 kHz Sample
Frequency Control.
11 AGND I Analog Ground
12 OUTR+ O Right Channel Positive line level analog output.
13 OUTR- O Right Channel Negative line level analog output.
14 FILTR O Voltage Reference Filter Capacitor Connection.
Bypass and decouple the voltage reference
with parallel 10 µF and 0.1 µF capacitors to the
AGND.
FUNCTION
PIN
NAME I/O
NO.
15 AGND I Analog Ground
16 OUTL- O Left Channel Negative line level analog
output.
17 OUTL+ O Left Channel Positive line level analog
output.
18 AVDD I Analog Power Supply. Connect to analog 5
V supply.
19 FILTB O Filter Capacitor connection, connect 10 µF
capacitor to AGND.
20 IDPM1 I Input serial data port mode control one.
With IDPM0, defines one of four serial
modes.
21 IDPM0 I Input serial data port mode control zero.
With IDPM1, defines one of four serial
modes.
22 ZEROL O Left Channel Zero Flag Output. This pin
goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.
23 MUTE I Mute. Assert HI to mute both stereo analog
outputs. Deassert LO for normal operation.
24 /PD//RST I /Power-Down//Reset.
placed in a low power consumption mode
when this pin is held LO. The AD1854 is
reset on the rising edge of this signal. The
serial control port registers are reset to the
default values. Connect HI for normal
operation.
25 L//RCLK I Left//Right clock input for input data. Must
run continuously.
26 BCLK I Bit clock input for input data. Need not run
continuously; may be gated or used in a
burst fashion.
27 SDATA I Serial input, MSB first, containing two
channels of 16, 18, 20, and 24 bits of twos
complement data per channel.
28 DVDD I Digital Power Supply Connect to digital 5 V
supply.
PSR-1000/PSR-2000
DM: IC700
FUNCTION
The AD1854 is
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