Denon AVR-3801 Service Manual page 23

QQ
3 7 63 1515 0
HY57V16160D (AU: IC417, 418)
V
1
DD
2
DQ0
DQ1 3
4
VssQ
DQ2
5
6
DQ3
7
V Q
DD
DQ4
8
9
DQ5
VssQ 10
11
DQ6
12
DQ7
V Q 13
DD
LDQM 14
15
WE
CAS 16
RAS 17
CS 18
A11 19
20
A10
A0 21
22
A1
23
A2
A3 24
V 25
DD
SN74AHCT573PW (AU: IC411)
SN74LV573ANS (AU: IC302, 412)
TE
L 13942296513
1 20
2 19
3 18
4 17
16
5
6 15
7 14
8 13
9 12
10 11
74VHC02MTC
(AU: IC410)
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Terminal Function
50 Vss
49 DQ15
Pin
DQ14
48
47 VssQ
CLK
46 DQ13
45
DQ12
CKE
V Q
44
DD
DQ11
43
CS
42
DQ10
BA
VssQ
41
40 DQ9
A0~A10
DQ8
39
V Q
38 DD
37 NC
RAS, CAS,
36 UDQM
WE
CLK
35
34 CKE LDQM,
NC
33 UDQM
32 A9
DQ0~DQ15
A8
31
V /Vss
DD
A7
30
29 A6
V /Vss
DDQ
A5
28
A4
27
NC
26 Vss
SN74AHCT08PW
(AU: IC421, 422)
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2 9
8
Pin Name
The system clock input. All other inputs are referenced to the SDRAM on
Clock
the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be
Clock Enable
one of the states among power down, suspend or self refresh
Chip Select Command input enable or mask except CLK, CKE and DQM
Bank Address Select either one of banks during both RAS and CAS activity
Row Address: RA0~RA10, Column Address: CA0~CA7, Auto-Pre charge
Address
flag: A10
Row Address Strobe,
RAS, CAS and WE define the operation.
Column Address
Refer function truth table for details
Strobe, Write Enable
Data Input/Output DQM control output buffer in read mode and mask input data in write
Mask mode
Data Input/Output Multiplexed data input/output pin
Power Supply/Ground Power supply for internal circuit and input buffer
Data Output
Power supply for DQ
Q
Power/Ground
No Connection No connection
Q Q
3 6 7 1 3 1 5
SN74LV14APW
(AU: IC530, 532)
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AVR-3801
9 4 2 8
Description
SN74LV00APW
(AU: IC408, 529)
0 5 8 2 9 9 4 2 8
MM74HCU04SJ
(RE: IC704)
m
9 9
9 9
23