Power Amplifier Section; High Speed Bias Servocontrol Circuit; Bias Circuitry Of Non-Switching Amplifier; Power Amplifier Circuit - Pioneer SX-3900 Service Manual

Power AmPlif ier Section
o Amplifier Circuit
The basic circuit arrangement of
the power
"-pilii"t
it shown in Fig' 4-5' The -first stage
is a
aiti*""ti"f
amplifier comprising PNP twin transis-
i.t
te2l, the load circuit
of which is a current
;*;;
employing an NPN twin transistor
(QB)'
Thecurrentmirrorprovidespush-pulloperationin
this stage, which serves to cancel even
harmonics
and further increase gain'
--
Qf in the input &cuit absorbs
outflow of base
current from Q2, and prevents the
generation of a
DC voltage. Because Q1 follows any
temperature
drift in Q2, temperature drift of
the center point
voltage is Prevented.
The pre-driver stage (Q4, Q5) is. a
Darlington
**g"-".rt,
the load circuit of which employs
a
constant-currentsource(Q6)resultingahighvolt-
age gain.
"
Tite power stage bias voltage is supplied
by the
high spe"a bias sewocontrol circuit'
The high
speea bias servocontrol circuit
provides non-
,^*it"t ing operation in the power stage
(refer to
;'High Speea Bias Servocontrol Circuit")'
The power stage (Q7
- Q12) is a.2-stage Darling-
ton arrangement, tite tinat stage
is parallel SEPP
circuit. Bicause there is no time constant
in the
NFB circuit in the low frequency region'
amplifi-
cation is possible down to DC (DC
inputs will be
""l.it,
however, by the input coupling capacitor)'
o High Speed Bias Servocontrol Circuit
By operating the power stage.only
within the
active region 1no possible cut-off).and
with mini-
mum idle current,'the high speed bias
servocontrol
circuit prevents the generation of switching
dis-
tortion and reduces heat loss'
This circuit is outlined in Fig' 4-6'
When there
is no signal applied to the circuit' Q1
and Q2 are
almost iut off' while Q3 and Q4 will
be on' The
uoitug" across the collector and base
of both of
these transistors (Q3 and Q4) at this
time may be
disregarded. Consequently, with the
power stage
||'.l *l
I
nl
bias circuit consisting of 4 PN
junctions formed by
Q3, D3 and Q4, and VR1'
--Witft
R1 and D1 ensuring a constart
flow of
current, the base of Q1 and
point X may be
brought to the same level on an
AC basis (level
f l u c t u a t i o n s d u e t o t h e s i g n a l ) b y a s i m p l e s h i f t i n
DC level. Furthermore, Q1 may
be considered
"-iti"t-toffower
with R3 as the emitter resistance'
-
When the voltage across points
Y and X is in-
creased by the positive portion
of th.e signal ap-
;i*i-;"
itrls cirluit, it becomel. the input
signal
it-trri,
emitter_follower (Q1). since
the emitter-
f o l l o w e r v o l t a g e g a i n i s p r a c t i c a l l y l , a v o l t a g e
m o r e o r l e s s e q u a l t o t h a t o f t h e i n p u t s i g n a l
iirr"i it, the voltage
increase across points Y and X)
ir^*"J"""a
at R5. And the R3 voltage
is the volt-
age applied across the base and
collector of Q3
which forms part of the power jt"g:
Pi"t
circuit'
il;h"
bias voltage applied to Q3 will
be in excess
by the same amou"i ttt" voltage
across points Y
and X increased (by positive
portion. of the signal)
above the voltage level when
no signal is being
applied. Consequently, the increase 1" l:]1"?:
lii"t.
o.i"ts
Y and X cancels the decrease rn
toii"g"'u"t"ss points X and Z't}r,ereby
maintaining
the idle current without cutiing
the PNP power
P R E - O R I V E R
t ' n . d - d
" e a s i "
C l r c , i t r v o f N o n - s w i t c h i n g A m p l i f i e r
P o w e r A m P l i f i e r C i r c u i t
F i s . 4 - 5