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1.4. BLOCK DIAGRAM
×Figure 1.1Ø
Data
Address
CPU
Control
60/66 MHz
CACHE
30/33 MHz
42C25
ICW
14.318 MHz CLOCK Generator
1.5. INTRODUCE THE PCI - BUS
Connecting devices to a CPU local bus can dramatically increase the speed of
I/O-bound peripherals with only a slight increase in cost over traditional systems.
This price / performance point has created a vast market potential for local bus
products. The main barrier to this market has been the lack of an accepted
standard for local bus peripherals. Many mainboard and chipset manufactures
developed their own local bus implementations, but they are incompatible with
each other. The VL (Video Electronics Standards Association) local bus and PCI
(Peripheral Component Interconnect) bus specification was created to end this
confusion.
The PCI - bus standard, under development since Jun. 1992, which is designed
to bring workstation-level performance to standard PC platform. The PCI - bus
removes many of the bottlenecks that have hampered PC for several years. On
the PCI - bus, peripherals operate at the native speed of the computer system,
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M1451
Control
RAS
CAS
MA
WE
DRAM
PCI
IDE
PCI BUS
IDE1
COM1
IDE2
7
ISA
SLOT1-4
M1449
PCI
SLOT1-3
UMC
I/O
ISA BUS
Floppy
LPT
COM2
Introduction
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