Block Diagram; Introduce The Pci - Bus - Pentium GA - 586IP User Manual

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1.4. BLOCK DIAGRAM

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Figure 1.1
Y2
HOST BUS
Data
CPU
Address
Pentium
Control
P54CT
Clock A
Clock B
CACHE
SRAM
Control

1.5. INTRODUCE THE PCI - BUS

Connecting devices to a CPU local bus can dramatically increase the speed of I/O-bound
peripherals with only a slight increase in cost over traditional systems. This
price / performance point has created a vast market potential for local bus products. The
main barrier to this market has been the lack of an accepted standard for local bus
peripherals. Many mainboard and chipset manufactures developed their own local bus
implementations, but they are incompatible with each other. The VL (Video Electronics
Standards Association) local bus and PCI (Peripheral Component Interconnect) bus
specification was created to end this confusion.
The PCI - bus standard, under development since Jun. 1992, which is designed to bring
workstation-level performance to standard PC platform. The PCI - bus removes many of the
bottlenecks that have hampered PC for several years. On the PCI - bus, peripherals operate
at the native speed of the computer system, thus enabling data transfer between peripherals
and the system at maximum speed. This performance is critical for bandwidth-constrained
devices such as video, multimedia, mass storage, and networking adapters.
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60 MHz Y3
PCI BUS
PCMC
Address/Data
82434
Clock E
Clock
Clock D
LBX
LBX
Control
82433
Clock C
Data Address
DRAM
14.318 MHz
EISA BUS
Address
SIO
Data
8 MHz Clock
82378
Control
PCI SLOT
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Introduction
ISA SLOT
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8042
BIOS