JVC KD-SX9350 Service Manual page 33

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4.8 LC75873NW(IC601):LCD Driver 3 7 63 1515 0
• Pin layout
• Pin function
Pin No. Pin name
79,80 S1/P1 to S4/P4
1,2,3 S5 to S68
to 66
67 COM1
78 COM2
69 COM3
74 OSC
TE
L 13942296513
76 CE
77 CL
78 DI
75 INH
71 VDD1
72 VDD2
70 VDD
73 VSS
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60 41
61 40
80 21
1 20
I/O
O Segment outouts for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as generalpurpose output ports under serial data control.
O Common driver outputs.
The frame frequency f0 is given by :
f0 = (FOSC/384)Hz.
I/O Oscillator connection
An oscillator circuit is formed by connecting an external resistor and capacitor to this pin.
I Serial data transfer inputs.
I Connected to the controller.
I CE:Chip enable
CL:Synchronization clock
DI:Transfer data
I Display off control input
• INH= "L"(VSS) ---Display forced off
S1/P1 to S4/P4 = "L"
(These pins are forcibly set to the segment output port function and held at the low level.)
S5 to S68 = "L"
COM1 to COM3"L"
• INH = "H"(HDD)---Display on
However, serial data transfer is possible when the display is forced off by this pin.
I Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VDD2 when a 1/2
bias drive scheme is used.
I Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VDD1 when a 1/2
bias drive scheme is used.
- Power supply connection. Provide a voltage of between 3.0 and 6.0V.
- Power supply connection. Connect to ground.
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• Block diagram
VDD1
VDD2
INH
OSC
VDD
VSS
Description
Q Q
3 6 7 1 3
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2 9 9 4 2 8
COMON
SEGMENT DRIVER
DRIVER
CLOCK
SHIFT REGISTOR
GENERATOR
ADDRESS
DETECTOR
1 5 0 5 8 2 9 9 4
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KD-SX9350,KD-SX990
9 9
2 8 9 9
(No.49781)1-33