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(12) Blank lamp control circuit
The blank lamp radiates light to the non-image area on the photocon-
ductor to discharge the void area in the copy lead edge and the
non-image area in reduction copy.
BL CLK
IC 116
IC 208
CPU
BL DATA
BL LATCH
BL BEO
To control BL (blank lamp), the following control lines are provided.
1 BLCLOCK: Serial transfer clock output
2 BLDATA:
Serial transfer data
Data is changed at clock rising.
Data is saved at clock falling.
3 BLLATCH: Data latch output
Data is changed at latch output rising.
Data is saved at latch output falling.
4 BLBEO:
Data output enable
Driver (data) is ON at "H."
Driver (data) is OFF at "L."
BLCLOCK
BLDATA
BLLATCH
ON
BLBEO
OFF
(Note) The output level definitions are at the CPU port.
(Relationship between reduction copy and the blank lamp)
Reduction ratio
×100% ~ ×96%
F ← 50 →
× 95% ~ ×92%
← 48 → FF
FF
× 91% ~ ×88%
← 46 → FFF
FFF
× 87% ~ ×84%
F ← 4 →F ← 44 →
× 83% ~ ×80%
F ← 5 →F ← 42 →
× 79% ~ ×76%
F ← 6 →F ← 40 →
× 75% ~ ×72%
F ← 7 →F ← 38 →
× 71% ~ ×68%
F ← 8 →F ← 36 →
× 67% ~ ×64%
F ← 9 →F ← 34 →
× 63% ~ ×59%
F ← 10 →F
× 58% ~ ×56%
F ← 11 →F
× 55% ~ ×52%
F ← 12 →F
× 51% ~ ×50%
F ← 13 →F
BL PWB
Controller
LATCH
BL state (F: ON, :OFF)
F← 4 → F
F← 5 → F
F← 6 → F
F← 7 → F
F← 8 → F
F← 9 → F
← 32 → F← 10 → F
← 30 → F← 11 → F
← 28 → F← 12 → F
← 26 → F← 13 → F
4. Operation circuit
General
•
The operation circuit is composed of the key matrix circuit and the
display circuit.
<Key circuit>
BL
(1) Block diagram
To CPU
OUT
(Output)
Operation
conterol
(2) Key detection
Key detection is performed by the key detection IC (LR3717M) with
matrix of S0 ~ S7 and K0 ~ K6. Information is set to the CPU by serial
data transmission. (& x 8 matrix available)
CPU
LM339NS
Operation control
ON
The transmission system is PPM (Pulse Position Modulation) system
using 15 bit data pulse signals.
The PPM transmission makes distinction of pulse width as logic "1" or
logic "0."
F
As shown above, when the pulse interval is T, the pulse is judged as
logic "1," and when the pulse interval is T/2, it is judged as logic "0."
Pulse signals of 15 bits are serially sent.
PPM signal is judged from pulse interval "t" as shown below:
When t < 0.4 m
When 0.4 ms < t < 1.6 ms : "0"
When 1.6 ms < t < 3.2 ms : "1"
When 3.2 ms < t
13 – 9
IC
LR3717M
S0~S7,K0~K6
5V
S7
Output
Serial data
LR3717M
T
T/2
: Abnormal
: Abnormal
Key
matrix
section
S0
K0
IC
K6
Matrix section
Logic"1"
Logic"0"
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