GX15
IC601 VHIXC621918-1L (XC621918): REGULATOR
Pin No.
Terminal name
1
VIN
2*
NC
3
VOUT
4*
NC
5
VSS
6
CE
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
IC603 (LR38876): CAMERA I/F CONVERSION LSI
Pin No.
Terminal name
1*
–
2
EXCKI
3
GND
4
A19
5
A2
6
WRB
7
GND
8
OD9
9
OD10
10*
–
11
GND
12
CVDD
13
A18
14
A1
15
RDB
16
HVDD2
17
OD8
18
OD11
19
TEST5
20
OD7
21
OD13
22
OD12
23
OD6
24
OD5
25
A17
26
CSB
27
OD15
28
OD14
29
OD3
30
OD2
31
OD4
32
TEST4
33
CLKO
34
GND
35
OD0
CONFIDENTIAL
Input/Output
Input
Input
–
Not used
Output
Output
–
Not used
–
Earth
Input
ON/OFF Control
ON/OFF
6
CE
Control
-
+
Input/Output
–
Continuity test terminal (Not used)
Input
System clock input
–
Earth
Input
CPU I/F address
Input
CPU I/F address
Input
CPU I/F write signal input
–
Earth
Input/Output
CPU I/F data bus, bit 9
Input/Output
CPU I/F data bus, bit 10
–
Continuity test terminal (Not used)
–
Earth
–
Internal core power supply (+1.8 V)
Input
CPU I/F address
Input
CPU I/F address
Input
CPU I/F read signal input
–
External digital power supply 2 (+1.8/3.0 V)
Input/Output
CPU I/F data bus, bit 8
Input/Output
CPU I/F data bus, bit 11
Input
Test terminal 5
Input/Output
CPU I/F data bus, bit 7
Input/Output
CPU I/F data bus, bit 13
Input/Output
CPU I/F data bus, bit 12
Input/Output
CPU I/F data bus, bit 6
Input/Output
CPU I/F data bus, bit 5
Input
CPU I/F address
Input
CPU I/F chip select input
Input/Output
CPU I/F data bus, bit 15
Input/Output
CPU I/F data bus, bit 14
Input/Output
CPU I/F data bus, bit 3
Input/Output
CPU I/F data bus, bit 2
Input/Output
CPU I/F data bus, bit 4
Input
Test terminal 4 (use Low input)
Output
Output clock to camera module
–
Earth
Input/Output
CPU I/F data bus, bit 0
Description of terminal
1
Each circuit
Current
Limit
3 VOUT
R2
R1
Voltage
5
Reference
Description of terminal
6 – 16
VIN
VSS