Circuit Description - ViewSonic VS11425 Service Manual

20” color tft lcd display
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4. Circuit Description

RTD2553V
LCD Monitor/MFM Controller
General
  E mbedded dual DDC with DDC1/2B/CI
 
  Z oom scaling up and down
 
  N o external memory required.
 
  R equire only one crystal to generate all timing.
 
  P rogrammable 3.3V/5V detection reset
 
  E mbedded crystal output to micro
 
  3 channels 8 bits PWM output, and wide range
 
Analog RGB Input Interface
  I ntegrated 8
-bit triple-channel 210/165 (optional) MHz ADC/PLL
 
  E mbedded programmable Schmitt
 
  S upport Sync On Green (SOG) and various kinds
 
  O n
-chip high-performance hybrid PLLs
 
  H igh resolution true 64 phase ADC PLL
 
  Y /Pb/Pr support up to HDTV 1080i resolution
 
  S upport 2/1 Analog input (optional
 
Digital Video Input Interface
  S upport 8
-bit video (ITU 656) format input
 
  S upport 16
-bit video (ITU 601) format input (optional)
 
  B uilt
-in YUV to RGB color space converter & de-interlace
 
DVI Compliant Digital Input Interface (optional)
  S ingle l
ink on-chip TMDS receiver
 
  S upport to 165Mhz with long cable
 
  A daptive algorithm for TMDS capability
 
  D ata enable only mode support
 
  H igh
-Bandwidth Digital Content Protection (HDCP 1.1) (optional only in H version)
 
  E nhanced protection of HDCP se
 
Auto Detection /Auto Calibration
  I nput format detection
 
  C ompatibility with standard VESA mode and
 
  S mart engine for Phase/Image position/Color
 
Scaling
  F ully programmable
 
  I ndependent horizontal/vertical scaling
 
  A dvanced zoom algorithm provides high image
 
  S harpness/Smooth filter enhancement
 
  S upport non
 
Vivid Color.
  D ynamic Contrast Control (DC
 
  I ndependent Color Management (ICM)
 
  T rue 10 bits color processing engine
 
  s RGB compliance
 
  A dvanced Dithering logic for 18
 
  D ynamic overshoot
 
  B rightness and contrast control
 
  P rogr
ammable 10-bit gamma support
 
Output Interface
  F ully programmable display timing generator
 
  F lexible data pair swapping for easier system
 
  P rogrammable TCON function support
 
  M ulti
-output interface (RSDS/LVDS/TTL)on single PCB
 
  S pread
-Spectrum DPLL to reduce EMI
 
  F ixed Last Line output for perfect panel
 
Host Interface
 S upport MCU serial/parallel bus interface.
 
 S upport MCU dual edge data latch.
 
ViewSonic Corporation
-controller.
trigger of HSYNC
)
cret key (optional only in H version)
zoom ratios
-linear scaling from 4:3 to 16:9 or 16:9 to 4:3
C)
-bit panel color depth enhancement
-smear canceling engine
output.
selectable PWM frequency.
of composite sync modes
support user-defined mode
calibration
quality
design.
capability
17
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VG2030wm-1

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