IBM 5150 Technical Reference page 34

control lines, memory refresh timing control lines, a
channel-check line, and power and ground for the adapters. Four
voltage levels are provided for I/O cards: +5 Vdc, -5 Vdc, + 12
Vdc, and -12 Vdc. These functions are provided in a 62-pin
connector with 100-mil card tab spacing.
A 'ready' line is available on the I/O channel to allow operation
with slow I/O or memory devices.
If
the channel's ready line is
not activated by an addressed device, all
microprocessor-generated memory read and write cycles take four
21O-ns clocks or 840-ns/byte. All microprocessor-generated I/O
read and write cycles require five clocks for a cycle time of
1.05-.us/byte. All DMA transfers require five clocks for a cycle
time of 1.05-.us/byte. Refresh cycles occur once every 72 clocks
(approximately 15-.us) and require four clocks or approximately
7 % of the bus bandwidth.
I/O devices are addressed using I/O mapped address space. The
channel is designed so that 512 I/O device addresses are available
to the I/O channel cards.
A 'channel check' line exists for reporting error conditions to the
~
microprocessor. Activating this line results in a non-maskable
interrupt (NMI) to the 8088 microprocessor. Memory expansion
options use this line to report parity errors.
The I/O channel is repowered to provide sufficient drive to power
all five system unit expansion slots, assuming two low-power
Schottky loads per slot. The IBM I/O adapters typically use only
one load.
System
Board 1-1 S