Block Diagram - Sanyo LCD-32E30A Service Manual

IC block diagram
1. Zoran ZR39670
Feature:
Embedded High Performance 300MIPS CPU
Integrated MIPS 4KEc
Intended to run RTOS, audio decode and Application software
32-bit MIPS32 enhanced architecture
8 K instruction cache, 8 K data cache, (2-way set associative)
MMU with 16-dual entry (TLB)
Integrated HDMI Link and PHY
Two Independent instances of the PHY
Support for HDMI v1.3
Integrated Secure HDCP Keys
Integrated HD ADC
Three YPbPr inputs (Two SCART)(Up to 1080p)
One RGB input (Up to WUXGA)
Up to 165 MHz input bandwidth
High-Performance MPEG-2 Video Decoding Engine
Support for a single MP@HL decoder
Integrated Dual Channel LVDS Output for direct Panel Display support
Supports up to 165MHz
1080p Output Flat Panel Support
100/120 Hz Operation with 768p panels
6, 8, 10 and 12-bit panel support
Integrated NTSC/PAL/SECAM Decoder
SCART Support
Fast Blank/Fast switch inputs
Video DAC for CVBS output
Display Processor & Controller
PIP operation with Digital/Analog PIP
Common Interface (CI)
Integrated USB 1.1 Interface
System Interfaces
Two 2-signal UARTs
Three I2C master or Slave interfaces (up to 400 kb/s)
One IR Receive, with hard N are demodulation
Guest bus interface
SPI interface
Device Unique Chip ID
128-bit device unique secret key
Memory Interface Unit
High performance 32-bit DDR2 interface (400MHz)
Up to 3.2GByte/second peak memory throughput
Process Technology
80 nm CMOS
Power
1.1 V core voltage 1.8 V Memory I/F, 3.3 V I/O
Packaging
35 mm x 35 mm Plastic Ball Grid Array package
632 BGA
CPU, 300MHz
TM
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