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ELAN DIGITAL SYSTEMS LTD. HD717 User Manual

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ELAN DIGITAL SYSTEMS LTD.
e-mail: support@elan-digital-systems.co.uk
HD717 PC-CARD USER'S GUIDE
ISSUE
PAGES
1
59
2
60
3
60
4
58
5
58
6
52
7
52
8
52
9
52
10
52
11
55
Elan Digital Systems Ltd.
GUIDE
LITTLE PARK FARM ROAD,
SEGENSWORTH WEST,
FAREHAM,
HANTS. PO15 5SJ.
TEL: (44) (0)1489 579799
FAX: (44) (0)1489 577516
website: www.pccard.co.uk
ALSO COVERS HD712,HD713
REVISION HISTORY
DATE
11.04.97
28.04.97
09.09.97
28.01.98
25.03.98
24.07.98
10.08.98
16.04.99
29.01.01
11.04.02
23.04.02
1
NOTES
FIRST ISSUE
NEW FEATURES
SCC DATA/CLK TIMING NOTE p15
SIMPLIFY PCCARDGO TEXT
RS422 ENABLE BIT (GSR2)
REMOVED SOFTWARE SECTION
TO PCCARDGO.DOC
HD712 ADDED
HD713 ADDED
LOOPBACK CONNECTIONS
LOOPBACK CONNECTIONS
Figure 3.1.3-1 Added
HD717 USER'S

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  • Page 1 ELAN DIGITAL SYSTEMS LTD. LITTLE PARK FARM ROAD, SEGENSWORTH WEST, FAREHAM, HANTS. PO15 5SJ. TEL: (44) (0)1489 579799 FAX: (44) (0)1489 577516 e-mail: support@elan-digital-systems.co.uk website: www.pccard.co.uk HD717 PC-CARD USER’S GUIDE ALSO COVERS HD712,HD713 REVISION HISTORY ISSUE PAGES DATE NOTES 11.04.97 FIRST ISSUE 28.04.97...

  • Page 2: Table Of Contents

    3.1.3 SCC TX/RX CLOCK SELECTION ............14 3.1.4 SCC TRANSMIT PROCEDURE ..............17 3.1.5 SCC RECEIVE PROCEDURE..............21 3.1.6 RS485 SUPPORT (Issue 2(+) HD717 & HD712,713 Cards Only) ..... 23 3.2 LOW RATE DATA ..................24 3.2.1 TRANSMIT....................24 3.2.2 RECEIVE ..................... 28 3.3 HANDLING INTERRUPTS................
  • Page 3 5.2 POWER CONSUMPTION................53 5.3 MECHANICAL ....................53 5.4 ENVIRONMENTAL..................53 5.5 LOOP BACK CONNECTIONS FOR TEST SOFTWARE ......53 6. SOFTWARE....................54 6.1 UNIVERSAL DRIVER..................54 6.2 C SOURCE CODE ................... 54 7. OPERATIONAL PRECAUTIONS .............55 Elan Digital Systems Ltd. HD717 USER’S GUIDE...
  • Page 4 Elan assume no liability for any direct or indirect losses arising from use of the supplied code. Copyright © 1996,1997 Elan Digital Systems Ltd. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 5: Overview

    Elan will be happy to quote for either customisation of the HD717 if its exact specifications do not quite meet your needs, or to create complete application software.

  • Page 6: About The Hd717

    The only fundamental difference in the way the SCC operates on the HD717 is that the data for TX and RX is buffered by 4096 x 8 FIFOs. On an ISA card, it is common to use the SCC in DMA mode, where two DMA channels are used (one for TX and one for RX data paths).

  • Page 7: Low Rate Data Interfaces

    HD712 / Iss2.01+ HD717 Figure 2.1-1 Functional Block Diagram of SCC + FIFOs 2.2 LOW RATE DATA INTERFACES The HD717 provides inputs and outputs for two of the common ARINC 717 serial data protocols, namely Bipolar Return-to-Zero and Harvard Biphase (or FM1).
  • Page 8 The HD717 provides a status bit and various control Elan Digital Systems Ltd.

  • Page 9: Digital I/O Interface

    (i.e. very long cables). 2.3 DIGITAL I/O INTERFACE 8 Digital I/O drivers are provided on the HD717 to use as general purpose control outputs and/or status monitoring inputs. The I/O pins are logically grouped together in clusters of 1,1,2,4 I/O pins (i.e.

  • Page 10: Controlling The Hd717

    3. CONTROLLING THE HD717 3.1 SCC 3.1.1 SCC I/O PORTS The control registers of the SCC are mapped for read and write at IOBASE+0. The data registers (i.e. TX and RX data buffers) are mapped at IOBASE+1. It is not recommended to directly access the SCC data registers unless you intend to run the serial data at very low rates.

  • Page 11: Scc Basic Configuration

    3.1.2 SCC BASIC CONFIGURATION The following table shows the required SCC set-up to enable the HD717 to operate correctly. Bits marked as ‘0’ or ‘1’ must be as such, those marked as ‘x’ can take a state appropriate to the configuration needed.
  • Page 12 When using DPLL, observe the maximum data rates (Zilog data sheets) for the SCC to be able to recover the clock from the data stream. See also the HD717 SCS register for the external clock selection options. xxxxxxxx = xxh...
  • Page 13 Use to access WR7 or WR7' No zero count int on BRGen Enable status FIFO in SCC No DCD int No SYNC/hunt int No CTS int Enable int on TX underrun/EOM Enable int on RX break/abort Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 14: Scc Tx/Rx Clock Selection

    3.1.3 SCC TX/RX CLOCK SELECTION As well as being able to select various clock sources for the SCC via WR11, the HD717 also pre-muxes both the TX and RX clocks to allow even greater flexibility on how the card is used in synchronous systems.
  • Page 15 0: DISABLE TX & RX clocks to SCC. When enabled, the TRxC and RTxC pins are driven from the HD717 derived clock or from the off-card clock inputs. For the HD712/713 and Iss2.01+ HD717 cards this bit serves an...
  • Page 16 In a synchronous system there must be sufficient setup and hold time for the data relative to the clock. In the external clock case, the HD717 passes clock and data through the same type of RS422 receiver / transmitter chips. This means that no significant extra skew between clock and data is added.

  • Page 17: Scc Transmit Procedure

    1. The SCC signals that it has completed the message (EOM) 2. The HD717 signals that the TX 4K FIFO has fallen below half full (only applies if original message was 2048 or more bytes long) 3. The HD717 signals that the TX 4K FIFO has fallen to empty The HD717 will cease to acknowledge TX DMA requests from the SCC when the TX 4K FIFO is empty.
  • Page 18 Remember that before re-loading the TX 4K FIFO with the next message to send, the HD717 TX DMA must be disabled. If this is not done the HD717 will start honouring TX DMA requests as soon as the FIFO holds data and there is a possibility (at high bit rates) that the SCC will empty the TX 4K FIFO faster than it is being filled by the PC.
  • Page 19 PCR2 TXDMAEn: Set to ‘1’ to allow the HD717 TX DMA controller to honour SCC TX DMA requests. The TX DMA controller will only “run” if the TX 4K FIFO contains >0 bytes of data. IMR0 MaskSCCInt: Set to ‘1’ to mask interrupts from the SCC.
  • Page 20 SCC underflow and terminate the frame prematurely). Accessing (reading) one SCC register every 50us is OK; every 1us is not ! Also bear in mind that the situation gets worse if the HD717 is both transmitting AND receiving data at the same time. Again the arbitrator is working to share the bus between all sources and so the potential to “run out of time”...

  • Page 21: Scc Receive Procedure

    RX 4K FIFO 2. The SCC signals that it has a special condition or error 3. The HD717 signals that the RX 4K FIFO has risen above half full and needs to be emptied of at least 2K of data.
  • Page 22 FIFO ! In such a case, use only the single 2K block read and then exit the ISR. HD717 control / status registers that relate to an SCC RX are listed below: REGISTER BIT...

  • Page 23: Rs485 Support (Issue 2(+) Hd717 & Hd712,713 Cards Only)

    See the SCC TX section for details on accessing the SCC’s registers whilst receiving data into the RX 4K FIFO. 3.1.6 RS485 SUPPORT (Issue 2(+) HD717 & HD712,713 Cards Only) The HD717 uses RS422/485 line drivers for all signals associated with the SCC.

  • Page 24: Low Rate Data

    3.2.1 TRANSMIT The HD717 can transmit Low Rate Data (or LRD) in various formats and at a range of baud rates. The HD717 uses a parallel to serial (p-to-s) converter and a holding register to maintain a continuous data stream under interrupt control. The word size for the holding register is 12-bits (ARINC 717).
  • Page 25 Pins 17 & 18 (BRZOUTa/b), and FM0 and FM1 are on Pins 19 & 20 (HVDOUTa/b). The baud rate is set using a programmable divider in the HD717. The formula for the baud rate is given by: LRD Baud Rate = 16x10 / (868 * ((LBG &...
  • Page 26 This means that unmasking an interrupt is different to using the MIRQEn bit in the PCR to “block” interrupts. The above procedure requires interrupts to be unmasked. Elan Digital Systems Ltd. HD717 USER’S GUIDE...
  • Page 27 HD717 control / status registers that relate to LRD TX are listed below: REGISTER BIT FUNCTION PCR0 MIRQEn: Set to ‘1’ to allow any interrupt through to the PC PCR1 IRQInService: Use this bit in the ISR routine to lock the IRQ state, so indicating that an IRQ is being serviced by software.

  • Page 28: Receive

    3.2.2 RECEIVE The HD717 can receive Low Rate Data (or LRD) in various formats and at a range of baud rates. The HD717 uses a serial to parallel (s-to-p) converter and a holding register to maintain a continuous data stream under interrupt control. The word size for the holding register is 12-bits (ARINC 717).
  • Page 29 HD717 behaves prior to this synchronised state and one status bit to determine when sync has been achieved. See below for details. HD717 control / status registers that relate to LRD RX are listed below: REGISTER BIT FUNCTION PCR0 MIRQEn: Set to ‘1’...
  • Page 30 Also expect the FM and BRZ modes to show different relative delays. The HD717’s FM decoding can tolerate duty cycle errors of up to 5% i.e. 45% to 55% duty cycle (for an FM encoded bit) and additionally up to 2% error in the nominal bit rate.

  • Page 31: Handling Interrupts

    3.3 HANDLING INTERRUPTS The HD717 has six possible sources of interrupt as detailed below: Interrupt Source Status on Mask with IPR0 IMR0 LRD TX IPR1 IMR1 LRD RX IPR2 IMR2 TX 4K FIFO FALLEN IPR3 IMR3 BELOW HALF FULL RX 4K FIFO RISEN...
  • Page 32 The following is a pseudo code shell for an ISR for the HD717. It does not attempt to embody all the subtleties of configuring the SCC. This aspect is application specific and so is only shown in a “notional” form assuming SDLC mode. See [REF 1] for complete details.
  • Page 33 //CRC error within frame ? SCCErrorTrap(CRCERROR); else if (RR0 & 0x40) //TX end of message ? TXEndOfMessageFlag = TRUE; //signal message done else if (IPR & TXFIFOEIntPendingBit) //TX FIFO now empty TXEndOfMessageFlag = TRUE; //signal message done Elan Digital Systems Ltd. HD717 USER’S GUIDE...
  • Page 34 IMR register bits. In some conditions, the IMR bits are also used to clear a pending interrupt by setting a bit to ‘0’ ‘1’ ‘0’ in software. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 35: Using The Digital I/O Pins

    3.4 USING THE DIGITAL I/O PINS The HD717 has eight digital I/O pins for general control and status use. The data used to drive I/O pins configured as outputs is written via the DIDO[7:0] register. The bit position significance for this register with the DIOPin number is one-for-one i.e.

  • Page 36: Hd717 Register Interface

    CIS EPROM to 0-3FF,800-BFF etc. in attribute space. The range 400-7FF is occupied by the PCMCIA config option register inside the HD717 (it repeats every byte). Both the CIS and COR are always active. The COR is used as a master enable, as defined by PCMCIA 2.01.
  • Page 37 The following table shows the indexes of the various sub-registers in the HD717 (all are 8-bits unless stated): SUB REG SUB REG read SUB REG write IDX[3:0] PRIMARY CONTROL PRIMARY CONTROL PCR[7:0] PCR[7:0] REGISTER REGISTER LOW RATE DATA BAUD LOW RATE DATA BAUD...

  • Page 38: Scc Control (Iobase+0)

    SCC TX DATA SCC RX DATA SCC TX DATA SCC RX DATA Neither of these ports should need to be accessed directly. Instead, use the TX & RX 4K FIFOs mapped at IOBASE+7. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 39: Ipr Read / Imr Write (Iobase+2)

    NOT USED Write 0 Reads as 0 This is the Interrupt Mask This is the Interrupt Pending Register for the HD717. It can Register for the HD717. be read at SUB REG IDX 7. Elan Digital Systems Ltd. HD717 USER’S...

  • Page 40: Lrd Rx Lo Read / Tx Lo Write (Iobase+3)

    Write 0 Reads as 0 This port is the high nibble This port is the high nibble read write port for the TX Low Rate port for the RX Low Rate Data. Data. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 41: Sub Reg Data (Iobase+5)

    SUB REG IDX RESERVED Write 0 NOT USED Write 0 NOT USED Write 0 NOT USED Write 0 NOT USED Write 0 This port is the pointer to a sub register accessed via IOBASE+5. Elan Digital Systems Ltd. HD717 USER’S GUIDE...
  • Page 42 Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 43: Rx 4K Fifo Read / Tx 4K Fifo Write (Iobase+7)

    “feeds” the SCC with TX which is “fed” by the SCC with data. Access it ONLY with 8-bit RX data. Access it ONLY with wide port OUT commands. 8-bit wide port IN commands. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 44: Pcr (Sub Reg 0)

    4.9 PCR (SUB REG 0) RESE FUNCTION STAT WRITE READ MIRQEn IRQInService TXDMAEn RXDMAEn LRDMode0 LRDMode1 LRDMode2 LRDTXEn This register contains most of the important control bits for the HD717. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 45: Lbg (Sub Reg 1)

    Set this bit high to enable the LRD Baud Gen This register is the divider used to set the Low Rate Data baud rate. Bit7 acts as a master enable for the baud generator. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 46: Scs (Sub Reg 2)

    Clock rate select bit 0 Clock rate select bit 1 RESERVED TRxCEn EdgeSel (write 0) SCCPClkEn SCCTRClkEn (Also performs OSC selection on HD712,713 & Iss2.01+ HD717 cards) SCCTXClkExt SCCRXClkExt This register controls the SCC’s various clock inputs. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 47: Didi Read / Dido Write (Sub Reg 3)

    8 DIOPins. 4.13 DIR (SUB REG 4) RESE FUNCTION STAT WRITE READ DIOPin0 direction DIOPin1 direction DIOPin2,3 direction DIOPin4,5,6,7 direction DIOPull RESERVED RESERVED Write 0 RESERVED RESERVED Write 0 RESERVED RESERVED Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 48: Scr (Sub Reg 5)

    Write 0 RESERVED RESERVED Write 0 RESERVED RESERVED Write 0 RESERVED RESERVED Write 0 This register is the Secondary Control Register that contains miscellaneous control bits. * Implemented in Iss2 (or greater) cards. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 49: Msr Read Only (Sub Reg 6)

    TX 4K FIFO HALF FULL TX 4K FIFO FULL BAR RX 4K FIFO EMPTY BAR RX 4K FIFO HALF FULL RX 4K FIFO FULL BAR LRDRXSync NOT USED Reads as 0 This register contains miscellaneous status bits. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 50: Imr Read Only (Sub Reg 7)

    4.15 IMR READ ONLY (SUB REG 7) RESE FUNCTION STAT WRITE READ LRD TX LRD RX TX FIFO RX FIFO RESERVED RESERVED RESERVED This register is the readback for the Interrupt Mask Register. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 51: Hardware Specification

    DIGITAL I/O PIN 1 DIGITAL I/O PIN 2 DIOPin2 DIGITAL I/O PIN 3 DIOPin3 DIOPin4 DIGITAL I/O PIN 4 DIGITAL I/O PIN 5 DIOPin5 DIOPin6 DIGITAL I/O PIN 6 DIOPin7 DIGITAL I/O PIN 7 Elan Digital Systems Ltd. HD717 USER’S GUIDE...
  • Page 52 TOP OF CARD PIN 1 Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 53: Power Consumption

    PIN 18→ PIN 22 Additionally, the digital IOs should be cross-connected via 4K7 resistors as shown: PIN 25 →4K7→ PIN 29 PIN 26 →4K7→ PIN 30 PIN 27 →4K7→ PIN 31 PIN 28 →4K7→ PIN 32 Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 54: Software

    On the diskette provided are several .C and .H files that provide a convenient starting point for you to create your own application. The files are located in a directory with the same name as this card. Elan Digital Systems Ltd. HD717 USER’S GUIDE...

  • Page 55: Operational Precautions

    Likewise, don’t apply levels that are less than -0.5v to the digital inputs. • Don’t short circuit any of the HD717’s outputs to ground or to other outputs. This will damage the HD717. • Ensure that the card’s main 5v power input on the pcmcia 68 way connector does not exceed 7.0v as this will damage internal devices.

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