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ELAN DIGITAL SYSTEMS LTD.
e-mail: support@elan-digital-systems.co.uk
AD125 PC-CARD USER'S GUIDE
ALSO COVERS AD135, AD126, AD136, AD132, AD121, AD131
ISSUE
PAGES
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50
2
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3
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4
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5
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Elan Digital Systems Ltd.
LITTLE PARK FARM ROAD,
SEGENSWORTH WEST,
FAREHAM,
HANTS. PO15 5SJ.
TEL: (44) (0)1489 579799
FAX: (44) (0)1489 577516
website: www.pccard.co.uk
AND "MF2xx" SERIES CARDS
REVISION HISTORY
DATE
30.10.96
06.03.97
06.06.97
17.06.97
26.01.98
15.07.98
23.07.98
04.01.99
NOTES
FIRST ISSUE
CORRECTION TO SAMPLE RATE
CALCULATIONS
REDUCED LOAD LIMIT ON +/-15V
ADDED AD132
SIMPLIFY PCCARDGO TEXT & ADD
NOTE ABOUT PRE-RUN IN
SECTION 3.5.3
ADD AD121/131 & SEC 1.1. ALSO
SOME MINOR SPEC CHANGES IN
5.2.
REMOVED SOFTWARE SECTION
TO PCCARDGO.DOC
MF SERIES CARDS
1
AD125 USER'S GUIDE
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Table of Contents
Related Manuals for ELAN DIGITAL SYSTEMS LTD. AD135
Summary of Contents for ELAN DIGITAL SYSTEMS LTD. AD135
- Page 1 SEGENSWORTH WEST, FAREHAM, HANTS. PO15 5SJ. TEL: (44) (0)1489 579799 FAX: (44) (0)1489 577516 e-mail: support@elan-digital-systems.co.uk website: www.pccard.co.uk AD125 PC-CARD USER’S GUIDE ALSO COVERS AD135, AD126, AD136, AD132, AD121, AD131 AND “MF2xx” SERIES CARDS REVISION HISTORY ISSUE PAGES DATE NOTES 30.10.96 FIRST ISSUE 06.03.97...
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Page 2: Table Of Contents
CONTENTS 1. OVERVIEW....................4 1.1 MODEL NAMING CONVENTIONS..................5 2. ABOUT THE AD125 ..................6 2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION CONVERTERS ......6 2.2 NOISE............................6 2.3 POSSIBLE SOURCES OF MEASUREMENT ERROR............8 2.4 D to A Converters ......................... 9 3. CONTROLLING THE AD125..............10 3.1 ACQUISITION MODES...................... - Page 3 4.5 DIVHI / ADDRCTHI (IR 5)....................... 35 4.6 MUXSEQ (IR 6).......................... 36 4.7 TRIGTHRESH (IR 7) ........................ 36 4.8 CTLEN (IR 9) ..........................37 4.9 DECR (IR D) ..........................37 4.10 DECW (IR E) ..........................38 4.11 CLRCT (IR F)........................... 38 5.
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Page 4: Overview
1. OVERVIEW Before using the AD125, take some time to read the section “OPERATIONAL PRECAUTIONS”. The AD125 card is a general purpose Analogue Data Acquisition card with the following features: • 12-bit MSPS A to D converter (0.625MSPS FOR AD1x6) (0.25MSPS FOR AD132, 0.1MSPS FOR AD121/131) •... -
Page 5: Model Naming Conventions
1.1 MODEL NAMING CONVENTIONS The AD125 “family” of cards follows these naming conventions: “AD1[X][Y]” for A to D cards “MF2[X][Y]” for Multi-function A to D and D to A cards [X] “2” ⇒ 8 single ended channels “3” ⇒ 16 single ended channels [Y] “1”... -
Page 6: About The Ad125
2. ABOUT THE AD125 2.1 QUICK THEORY OF SUCCESSIVE APPROXIMATION CONVERTERS The type of converter used in the AD125 approximates the analogue level being applied to its input using a D to A converter and a comparator. The converter starts in “track” mode where it is following the input voltage and applying it to a track and hold amplifier. - Page 7 that the noise is Gaussian in distribution and is subject to the usual statistical spread in its peaks and troughs from moment to moment. So the converter output looks noisy, or at least more noisy than you might expect. Normally this is not a problem but occasionally some kind of post-processing of the data samples will be required in software.
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Page 8: Possible Sources Of Measurement Error
2.3 POSSIBLE SOURCES OF MEASUREMENT ERROR The following is a list of possible error sources that should be considered when taking measurements with the AD125: 1. The offset voltage of the A to D device and the front end electronics will mean that an input voltage of 0V will not produce an output code of 000000000000b. -
Page 9: D To A Converters
inside the AD125 at a “star-point”. All digital front-end circuits use a separate ground trace to the front-end analogue circuits to reduce such switching noise problems on the card itself. The AGND/GND link occurs at the PCMCIA 68-way connector. 6. If using the inputs in differential mode, do not forget to keep the common mode signal within the common mode range of the AD125s inputs. -
Page 10: Controlling The Ad125
3. CONTROLLING THE AD125 3.1 ACQUISITION MODES In all modes, the AD125 performs its conversions in around 2.0µs (1.66µs for the AD1x6). The conversion rate is software programmable and is achieved by “spreading-out” the conversions using the PACER clock. 3.1.1 BURST MODE This is the mode intended for transient capture or vibration analysis. -
Page 11: Fifo Mode
3.1.2 FIFO MODE This is the mode intended for streaming data into the PC at high speed. Summary: The AD125 takes continuous conversions in this mode. There is no triggering. As soon as software sets RUN to on, the SRAM starts to fill. -
Page 12: A To D Output Format / Gain Setting
3.2 A to D OUTPUT FORMAT / GAIN SETTING The AD125 produces 2’s complement 12 bit output codes when in Bipolar mode and “true binary” 12 bit codes when in Unipolar mode. Table 3.2-1 summarises the codes. THEORETICAL AD125 OUTPUT CODE INPUT LEVEL BIPOLAR UNIPOLAR... - Page 13 20 different input ranges can be achieved with the AD125. The gain is programmed using the top four bits of SETUP REG 1 (GS0..3). The following table summarises the gains and input ranges available: GAIN GS0..3 AD125 INPUT VOLTAGE RANGE (volts) BIPOLAR UNIPOLAR 0 →...
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Page 14: Ad125 Buffer Addressing
3.3 AD125 BUFFER ADDRESSING 3.3.1 BUFFER DATA ORDER The AD125 always writes its A to D conversion samples into the SRAM buffer. They can be read out directly by the PC software. 2 bytes of data get written to the SRAM for every conversion “event”. The buffer is organised as follows: Pointer Address Decreasing →... -
Page 15: Pre-Trigger Depth
To decrement the WRITE POINTER by TWO, do a write access to the DECW port with don’t care data. Remember that in FIFO mode, you may get an IREQ when changing the WRITE POINTER through a half or quarter count (just as you would if the AD125 passed these points whilst running at full speed...use the SELCTRD bit to block interrupts whilst manipulating the WRITE POINTER if this is a problem...see section on interrupts). -
Page 16: Reading The Sram Data
Remember that you must control the RUN and ENTRIG bits correctly to ensure that the pre-trigger buffer actually holds valid conversion data: the AD125 could trigger before conversion results have been written into the whole pre-trigger area of SRAM. The rule is to set the AD125 into RUN mode but with ENTRIG off, in software wait a minimum of (t x n) seconds before enabling trigger (t is the sample period, n is the pre-trigger depth in conversions). -
Page 17: Triggering
3.4 TRIGGERING 3.4.1 THRESHOLD The AD125 uses an 8-bit 2’s complement OR “true binary” trigger threshold value. This is compared against the top 8-bits of the 12- bits of A to D data to decide when to trigger the card. The value loaded into the threshold register MUST be appropriate to the conversion mode selected: 2’s complement for Bipolar, “true binary”... -
Page 18: Trigger Modes
3.4.2 TRIGGER MODES There are various configurations of trigger on the AD125, they are summarised below: > < TREDGE=1 LVL=0 TREDGE=0 LVL=0 TREDGE=1 LVL=1 TREDGE=0 LVL=1 TRIGGER WHEN TRIGGER WHEN TRIGGER TRIGGER I/P TRANSITIONS I/P TRANSITIONS WHENEVER I/P IS WHENEVER I/P IS FROM BELOW FROM ABOVE ABOVE Vtrig... -
Page 19: Enabling Trigger
3.4.3 ENABLING TRIGGER The AD125 will not trigger unless Bit 1 of SETUP REG 1 is low. This allows software to “arm” the AD125 only when it is appropriate to do so i.e. after some start up condition or when the user has signalled that the system should arm ready to capture an event. -
Page 20: Other Features
3.5 OTHER FEATURES 3.5.1 SAMPLE RATE The SAMPLE RATE is programmed via a 14-bit divider, accessed as an 8-bit register (DIVLO) and a 6-bit register (DIVHI). The clock divider runs at 5MHz. Additionally, there is an extra control bit that allows subtraction of a ¼... -
Page 21: Input Mux Control
3.5.2 INPUT MUX CONTROL There are 8 input channels to the AD12x and 16 to the AD13x. The channels can be used either in single ended mode i.e. number of input channels equals 8 (AD12x) or 16 (AD13x) OR they can be set to work in true differential mode giving 4 channels (AD12x) or 8 channels (AD13x). - Page 22 The following examples should clarify this: MUXSEQ REGISTER CHANNEL SEQUENCE SINGLE ENDED DIFFERENTIAL A1,A1,A1,A1..(A1- A5), (A1-A5), (A1- A5)..A6,A6,A6,A6..(A10-A14), (A10-A14), (A10-A14)..A11,A11,A11..INVALID A16,A16,A16..INVALID A5,A6,A7,A5,A6,A7..(A9-A13), (A10-A14), (A11- A15), (A9-A13), (A10- A14)..A12,A13,A14,A15,A16 INVALID ,A1,A2,A12,A13,A14, A15,A16..A16,A1,A16,A1,A16,A INVALID 1,A16..
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Page 23: Sleep Mode
3.5.3 SLEEP MODE The AD125 can be put into a low power SLEEP mode. This effectively shuts down the internal DC-DC converters, oscillator and AtoD converter. The analogue part of the card will not function in this mode. When enabling the card i.e. coming out of SLEEP mode, allow at least 2 seconds for the power to stabilise before taking any measurements. - Page 24 To actually use interrupts the HOST controller will have to be configured to route the IREQ signal to one of the PC’s interrupt channels. Note that all conditions that cause an interrupt can also be polled for in software; that is, you do not have to use interrupts. This is because the state of the internal Flip-Flop that latches the interrupt state can be read via IODIR REGISTER Bit 4: 0→INTERRUPT PENDING, 1→NO INTERRUPT.
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Page 25: Config Option Register
3.5.5 CONFIG OPTION REGISTER The AD125 uses the Config Option Register or COR to enable a particular mode. The COR is at 400h in attribute space and is 8-bits wide read/write. It is organised as follows: BIT0 Config value LSB BIT1 BIT2 BIT3... -
Page 26: Digital Io
3.5.6 DIGITAL IO There are 8 digital IO lines which can be used for general control / monitoring. The bottom 4 bits of the IODIR register are used to configure the IOPINs as inputs or outputs. The grouping is as follows: BIT0 DIRECTION OF IOPIN1 BIT1... -
Page 27: Dac Programming
3.6 DAC PROGRAMMING The DACs on the MF series are loaded serially using the upper four digital I/O lines (which are no longer accessible on the MF series). The following code fragment shows how to set DAC codes up: void EXPORTFUNCTION DLL_SetDtoACodes(unsigned char skt,unsigned short code1, unsigned short code2) //pass in either code as 0xFFFF to load previous DAC code... - Page 28 updates at a low rate. Due to the high overhead involved with loading DAC codes, DAC update rates of a few Hz can be realised. By setting the interrupt configuration of the FIFO run mode of the card this interrupt can occur i) every sample ii) every quarter buffer (i.e.
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Page 29: Ad125 Register Interface
4. AD125 REGISTER INTERFACE The AD125 decodes the incoming PCMCIA interface. It maps the CIS EPROM to 0-3FF,800-BFF etc. in attribute space. The range 400-7FF is occupied by the PCMCIA config option register inside the AD125 (it repeats every byte). Both the CIS and COR are always active. - Page 30 The following table shows the indexes of the various registers in the AD125 (all are 8-bits unless stated): DR write DR read SETUP REG 1 (8-BIT) SETUP REG 1 (8-BIT) SETUP REG 2 SETUP REG 2 IODATA IODATA IODIR (4-BIT) IODIR(6-BIT) DIVLO ADDRCTLO...
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Page 31: Setup Reg 1 (Ir 0)
4.0 SETUP REG 1 (IR 0) RESET FUNCTION STATE WRITE READ nRUN nRUN Set low to start the AD125 taking conversions or to start a SINGLE conversion. nENTRIG nENTRIG Set low to enable triggering i.e. ARM the AD125 (BURST mode only). -
Page 32: Setup Reg 2 (Ir 1)
4.1 SETUP REG 2 (IR 1) RESET FUNCTION STATE WRITE READ IBITSEL0 IBITSEL0 See IBITSEL1. IBITSEL1 IBITSEL1 MSBit of 2-bit interrupt select: 00: Interrupt when buffer full ½ 01: Interrupt every buffer full ¼ 10: Interrupt every buffer full 11: Interrupt every conversion Only applies in FIFO mode. -
Page 33: Iodata (Ir 2)
4.2 IODATA (IR 2) RESET FUNCTION STATE WRITE READ IOPIN0 IOPIN0 Control IOPIN0 Status of IOPIN0 IOPIN1 IOPIN1 Control IOPIN1 Status of IOPIN1 IOPIN2 IOPIN2 Control IOPIN2 Status of IOPIN2 IOPIN3 IOPIN3 Control IOPIN3 Status of IOPIN3 IOPIN4 IOPIN4 Control IOPIN4 Status of IOPIN4 IOPIN5 IOPIN5... -
Page 34: Iodir (Ir 3)
4.3 IODIR (IR 3) RESET FUNCTION STATE WRITE READ IOPIN0DIR IOPIN0DIR Set high to enable as OUTPUT IOPIN1DIR IOPIN1DIR Set high to enable as OUTPUT IOPIN2&3DIR IOPIN2&3DIR Set high to enable as OUTPUTS IOPIN4,5,6,7DIR IOPIN4,5,6,7DIR Set high to enable as OUTPUTS. On MF series the upper four IOs WFGEN are always outputs and this bit... -
Page 35: Divlo / Addrctlo (Ir 4)
4.4 DIVLO / ADDRCTLO (IR 4) RESET FUNCTION STATE WRITE READ DIV0 ADDRCT0 DIV1 ADDRCT1 DIV2 ADDRCT2 DIV3 ADDRCT3 DIV4 ADDRCT4 DIV5 ADDRCT5 DIV6 ADDRCT6 DIV7 ADDRCT7 LOW 8-BIT WORD OF 14-BIT LOW 8-BIT WORD OF 16-BIT CLOCK DIVIDER. SEE ALSO READ OR WRITE POINTER. -
Page 36: Muxseq (Ir 6)
4.6 MUXSEQ (IR 6) RESET FUNCTION STATE WRITE READ MUXSEQ0 (start address LSB) MUXSEQ1 MUXSEQ2 MUXSEQ3 (start address MSB) MUXSEQ4 (end address LSB) MUXSEQ5 MUXSEQ6 MUXSEQ7 (end address MSB) 8-BIT VALUE USED TO CONTROL INPUT MUX SEQUENCING. 4.7 TRIGTHRESH (IR 7) RESET FUNCTION STATE... -
Page 37: Ctlen (Ir 9)
4.8 CTLEN (IR 9) RESET FUNCTION STATE WRITE READ CTLEN0 CTLEN1 CTLEN2 CTLEN3 CTLEN4 CTLEN5 CTLEN6 7-BIT VALUE TO CONTROL ACTIVE LENGTH OF READ AND WRITE POINTERS. ALSO USED TO FORCE A PARTIAL RESET OF BOTH READ AND WRITE POINTERS. BIT-MAPPED: 0x7F SETS 15-BIT, 0x3F-14, 0x1F-13, 0x0F-12, 0x07-11, 0x03-10, 0x01-9, 0x00-8-BIT. -
Page 38: Decw (Ir E)
4.10 DECW (IR E) RESET FUNCTION STATE WRITE READ ANY READ OR WRITE ACCESS TO THIS PORT WILL DECREMENT THE WRITE POINTER BY TWO. 4.11 CLRCT (IR F) RESET FUNCTION STATE WRITE READ ANY READ OR WRITE ACCESS TO THIS PORT WILL SET THE READ &... -
Page 39: Hardware Specification
ANALOG CH 4 (CH 4 + IN DIFFERENTIAL MODE) ANALOG CH 8 (CH 4 - IN DIFFERENTIAL MODE) ANALOG CH 9 (CH 5 + IN DIFFERENTIAL MODE) A9 (AD135/6 ONLY) ANALOG CH 13 (CH 5 - IN DIFFERENTIAL MODE) A13 (AD135/6 ONLY) -
Page 40: Analogue
1% NOMINAL ACCURACY, 55ppm/oC DRIFT RESOLUTION: 12 BITS (11.2 AT NYQUIST) SAMPLE RATES: FROM 305SPS TO 500KSPS (AD125 & AD135) OR 625KSPS (AD126 & AD136) OR 250KSP (AD132) OR 100KSPS (AD121/131) (PROGRAMMABLE) IN SINGLE SHOT MODE SAMPLE RATES BELOW 305SPS ARE POSSIBLE. -
Page 41: Calibration Data
AD1x1, AD1x2 ≈ (4000 + 10 / Fin) Ω (SINGLE ENDED) INPUT IMPEDANCE: ! Avoid significant source impedance if you are digitising AC components with relatively high frequencies. To avoid attenuation > 1LSB the source impedance should be 4096 times less than the above calculated value. - Page 42 “<ZxxxU>” Zero point at gain xxx in Unipolar Mode “<FxxxU>” Full scale point at gain xxx in Unipolar Mode “<ZxxxB>” Zero point at gain xxx in Bipolar Mode “<FxxxB>” Full scale point at gain xxx in Bipolar Mode Zero point is defined in two ways : i) for Unipolar mode it is the voltage applied to the card that causes the ADC reading to be +½...
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Page 43: Digital
5.3 DIGITAL ALL PARAMETERS @ 25°C SAMPLE BUFFER: 32768 x 8 BITS (16K SAMPLES) ACQUISITION MODES: BURST, FIFO, SINGLE SHOT FIFO THROUGHPUT: > 500KSPS (PC SPEED DEPENDENT) DIGITAL I/O CHANS: 8 CHANNELS (AD) OR 4 (MF) BIT-MAPPED, PROG AS I/P OR O/P DIGITAL I/O DRIVE: 4mA TYP TO TTL LEVELS. -
Page 44: Software
6. SOFTWARE 6.1 UNIVERSAL DRIVER The PCCARDGO “universal driver” is used to act as a surrogate Card Services client for an end user application. This device driver simplifies greatly the enumeration process and configuration management task for your application. The driver is supplied on the diskette provided. Please refer to PCCARDGO.DOC for further information. -
Page 45: Operational Precautions
7. OPERATIONAL PRECAUTIONS Unless otherwise stated, all voltage levels are referenced to the AD125’s DIGITAL GROUND PIN. • Don’t leave active signals connected to the digital IOPINS that are capable of sourcing more than a few mA whilst the AD125 itself is unpowered.
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