Sundance Spas SMT327 User Manual
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Sundance Spas SMT327 User Manual

Sundance Spas SMT327 User Manual

Compact pci 4 slot motherboard
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Preliminary
SMT327
Compact PCI 4 SLOT MOTHERBOARD
User Guide
Document Name:
User Guide
Product Name:
SMT327
Author:
Bill Blyth
Issue : 01
Revision Date:
Original Date:
Rev 02
8 August, 2000
30 April 1998

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Summary of Contents for Sundance Spas SMT327

  • Page 1 Preliminary SMT327 Compact PCI 4 SLOT MOTHERBOARD User Guide Document Name: User Guide Issue : 01 Rev 02 Product Name: SMT327 Revision Date: 8 August, 2000 Author: Bill Blyth Original Date: 30 April 1998...

  • Page 2: Table Of Contents

    Preliminary Page 2 of 2 SMT327 User Guide SMT327 User Guide Contents 1. INTRODUCTION..................................4 1.1 F SMT327.............................4 EATURES OF THE 2. INSTALLATION..................................5 3. ARCHITECTURAL OVERVIEW ............................6 4. PATCH AREA ARCHITECTURE............................7 5. FRONT PANEL CONFIGURATION............................9 6. BUFFERED COMMUNICATION PORTS........................10 7.

  • Page 3: August

    Preliminary Page 3 of 3 SMT327 User Guide Figure 4 Master Mode Interface......................19 Document Name: User Guide Issue : 01 Rev 02 Product Name: SMT327 Revision Date: 8 August, 2000 Author: Bill Blyth Original Date: 30 April 1998...

  • Page 4: Introduction

    Page 4 of 4 SMT327 User Guide 1. Introduction This document is the user guide for the Sundance SMT327 TIM Carrier for CompactPCI. The board is 6U high and 8T wide (double width) to accommodate various TIM’s. 1.1 Features of the SMT327 •...

  • Page 5: Installation

    Note 62). TISLINK=SMT320,INDEX:0,DEVICE:0327. • A new 3L TIS loader program for Windows ‘95, TIS_WD32.EXE, is supplied with the SMT327. This must be copied into your 3L installation directory, usually TIC2V0: copy a:\tis_wd32.exe c:\tic2v2\tis.exe You will be requested if you wish to overwrite the original in this directory. This is required as the present version of TIS is not a protected mode program.

  • Page 6: Architectural Overview

    The SMT327 provides 4 TIM positions which can accommodate either single width or double width modules. A dedicated pipe is hard wired using communication ports 2 and 5 of each TIM, in common with the SMT320. In addition, all other communication...

  • Page 7: Patch Area Architecture

    4. Patch Area Architecture. The layout of the SMT327 is shown below. Two patch areas, upper and lower, allow each pair of TIM’s to be interconnected. Between these areas, three routing channels are provided to allow additional communication port connections between each pair of TIM’s.
  • Page 8 Preliminary Page 8 of 8 SMT327 User Guide Note that when connecting communication ports with the FMS cables, to ensure pin 1 is connected to pin 1 on the alternative communication port. One end of the cable must be inserted opposite to the other, i.e.

  • Page 9: Front Panel Configuration

    JTAG ports. In this case, a 20 way cable between a JTAG-IN and a JTAG-OUT is required. The SMT327 board designated as “ROOT” for 3L server purposes should also be the JTAG master with no connection to its JTAG-IN port.

  • Page 10: Buffered Communication Ports

    Twisted Pair Signal STRB DIR_OUT DIR_IN /RESET_OUT SPARE SHELL SHIELD Table 1 Buffered Communication Port Document Name: User Guide Issue : 01 Rev 02 Product Name: SMT327 Revision Date: 8 August, 2000 Author: Bill Blyth Original Date: 30 April 1998...

  • Page 11: Jtag Input & Output Ports

    Both input and output ports for JTAG are provided, designed to be compatible with the SMT328 and SMT301 motherboards. The JTAG interface is designed to operate at a maximum 10MHz across up to 4 SMT327 motherboards. By default this frequency is 8.33MHz (PCI_CLK/4) or less, depending on the PCI_CLK on the host.
  • Page 12 Preliminary Page 12 of 12 SMT327 User Guide Signal Direction Description JTAG data out JTAG data in JTAG Test mode select JTAG clock 10MHz TCK_RET JTAG clock return -TRST JTAG Reset -RESET Board Reset out Presence detect when pulled high...

  • Page 13: Fms Connectors (Internal Communication Ports)

    Note that these connectors have sense pins to detect when a cable is inserted. This avoids contention between the intended connection and the pipe. Document Name: User Guide Issue : 01 Rev 02 Product Name: SMT327 Revision Date: 8 August, 2000 Author: Bill Blyth Original Date: 30 April 1998...

  • Page 14: Registers

    SMT327 User Guide 9. Registers In target mode, the SMT327 is accessed by a host device across the PCI bus. This allows access to the target mode registers. The operating system or BIOS will normally allocate a base address for the target mode registers of each SMT327.

  • Page 15: Control Register (Offset 14H)

    Preliminary Page 15 of 15 SMT327 User Guide 9.2 Control Register (Offset 14h) The CONTROL register can only be written. It contains flags which control the boot modes of the first TIM site. Boot Control Name Not used notNMI IIOF2...

  • Page 16: Status Register (Offset 14H)

    Preliminary Page 16 of 16 SMT327 User Guide 9.3 Status Register (Offset 14h) The STATUS register can only be read. 31:22 Name CONFIG_L TBC RDY MASTER Name INTA Name C40 INT C40 IE TBC IE IBF IE OBE IE Set if comport output buffer empty interrupts enabled.

  • Page 17: Interrupt Control Register (Offset 18H)

    Preliminary Page 17 of 17 SMT327 User Guide 9.4 Interrupt Control Register (Offset 18h) This write-only register controls the generation of interrupts on the PCI bus. Each interrupt source has an associated enable and clear flag. This register can be written with the contents of bits 7:0 of the Status Register.
  • Page 18 Preliminary Page 18 of 18 SMT327 User Guide Offset (hex) Write Read Control0 Control0 Control1 Control1 Control2 Control2 Control3 Control3 Control4 Control4 Control5 Control5 Control6 Control6 Control7 Control7 Control8 Control8 Control9 Control9 Minor Command Minor Command Major Command Major Command...

  • Page 19: Bridge - C40 Operation

    10. Bridge - C40 Operation. The first TIM position on the SMT327 makes use of the global bus to allow the C40 to read and write the entire PCI address space. Burst mode and single transfers can be used to access the PCI address space.

  • Page 20: Pci Address

    Preliminary Page 20 of 20 SMT327 User Guide 10.2 8.2. PCI Address The PCI address register is a 30 bit counter loaded from bits D31:2 of the C40 data bus. The counter output is a 32 bit address with bits 1:0 always at logic 0.

  • Page 21: Physical Characteristics

    Preliminary Page 21 of 21 SMT327 User Guide 11. Physical Characteristics 11.1 Power Consumption This board requires both +5v and +3V3 from the CompactPCI connector. These must be provided to avoid damage to the PCI bridge. Without TIM’s the consumption from +5V is less than 3A and from +3V3 is less than 0.5A.

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