Sundance Spas SMT301A User Manual
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Sundance Spas SMT301A User Manual

Sundance Spas SMT301A User Manual

Vxi 8 slot motherboard
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SMT301A
VXI 8 SLOT MOTHERBOARD
User Guide
SU
MU T
SS T
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M T

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  • Page 1 SMT301A VXI 8 SLOT MOTHERBOARD User Guide MU T SS T...
  • Page 2 Disclaimer Every effort has been made to ensure the accuracy of this document, however the manufacturer cannot accept responsibility for any loss or damage caused as a result of using this document. Notice of any mistakes, inconsistencies or comments relating to this document would be gratefully received by fax to Sundance.

  • Page 3: Table Of Contents

    Sundance SMT301 User Guide TABLE OF CONTENTS Features Architectural Overview Global Bus Resources VXI Interface VXI Interface Registers Control and Status Registers Dual Port RAM (DPR) JTAG Debugging Logic Comm-port Interface 10. Reset Board Register 11. ‘C4x Memory Map 12. Communications Ports 13.

  • Page 4: Features

    SMT301 User Guide Sundance 1 Features Eight slot TIM motherboard Flexible communications port linking All 8 front panel comm-ports fully buffered Double pipe architecture - comm-ports unbuffered Global board resources 1MByte of one-wait-state SRAM accessible by TIM sites or VXI Memory expansion by daughter module (can be zero-wait-state) On board JTAG debugging circuit - accessed from VXI On board comm-port interface to VXI...

  • Page 5: Architectural Overview

    Sundance SMT301 User Guide 2 Architectural Overview This description should be read with reference to the diagram titled ‘VXI Motherboard Architecture’. Note that the layout of TIM sites on the board, is in the same order as shown in the diagram. buffer FIFO Bus High speed...

  • Page 6: Global Bus Resources

    SMT301 User Guide Sundance 3 Global Bus Resources There are two main global bus resources available on this motherboard. These are the bi-directional FIFO with its Hewlett Packard ‘Local Bus’ interface and the static Dual Port RAM (DPR). Mutually exclusive access to these resources can be made by either of the TIM sites which have a global bus connector (the two nearest the VXI connectors, sites 1 and 5).
  • Page 7 Sundance SMT301 User Guide for an external FIFO. The comm-port which is connected to this interface can be switched to either of the two TIMs which have global access (TIM1 or TIM5). A full duplex comm-port pipeline is hardwired between all of the TIMs, with TIM sites 1 and 5 as the pipeline ends.

  • Page 8: Vxi Interface

    SMT301 User Guide Sundance 4 VXI Interface The VXI interface uses the P1 connector and the centre row of the P2 connector for additional date and address lines. The interface forms a complete D8/16/32 master/slave. The card does not support slot 0 operation, block transfers or unaligned transfers.

  • Page 9: Vxi Interface Registers

    Sundance SMT301 User Guide 5 VXI Interface Registers The VXI specification defines a register block within A16 address space which is used for control, status and board set-up. These registers are shown below: Offset Register description ID register Device type Status / Control DPR Offset Sub-class Offset register...
  • Page 10 SMT301 User Guide Sundance Address 0xF800 = All on except switches 1,2,3. Address 0xFFC0 = All off. The VXI address modifiers must be set to 0x29 or 0x2D as these define an A16 transfer. VXI ID Register (00) The bit definitions for this register are: Definition 11..0 Manufacturer ID (set to 123 decimal...
  • Page 11 Sundance SMT301 User Guide Definition 0..1 Device dependent ( not used) Passed self tests (always asserted) Ready (connected to TIM CONFIG line) TIM config (normally read as C00C Hex) 5 .. 13 Device dependent ( not used) - MOD ID line status (inverted MOD ID) A32 active VXI Control Register (04) The bit definitions for the write only control register are:...
  • Page 12 SMT301 User Guide Sundance Definition 11..0 Manufacturer ID (set to 123 decimal) 14..12 Manufacturer sub-class (set to 001) 0 - normal Always reads as 107B hex. -10- 10 April, 1997...

  • Page 13: Control And Status Registers

    Sundance SMT301 User Guide 6 Control and Status Registers There are 5 control registers: Control Registers 1 and 2 = TIM Site 1 and 5 Interrupt Masks The FIFO flags can be programmed to produce an interrupt which goes to TIM sites 1 and 5.
  • Page 14 SMT301 User Guide Sundance Control Register 3 = VXI Interrupt Masks Each of the two TIM sites 1 and 5 can cause an interrupt to the VXI system. The interrupt level is selected by bits 12 ..10 of Control Register 4.. In addition to the IIOF0 lines causing a VXI interrupt, the FIFO flags can also generate a VXI interrupt.
  • Page 15 Sundance SMT301 User Guide Function 24 - 31 VXI address lines A24 to A31 during ‘C4x master cycle 18 - 23 Address modifier codes AM0 to AM5 during ‘C4x master cycle VXI LWORD during ‘C4x master cycle VXI A1 during ‘C4x master cycle Link interface switch control (0 = TIM site 1, 1 = TIM site 5) VXI bus request level bit 1 VXI bus request level bit 0...
  • Page 16 SMT301 User Guide Sundance Function TIM 5 IIOF0 TIM 1 IIOF0 VXI Bus Error (Latched) FIFO out full FIFO out almost full FIFO out almost empty FIFO out empty FIFO n full FIFO in almost full FIFO in almost empty FIFO in empty General Control Register 5 NOTE:...

  • Page 17: Dual Port Ram (Dpr)

    Sundance SMT301 User Guide 7 Dual Port RAM (DPR) The DPR is composed of 1MByte SRAM. This can be accessed as D8, D16 or D32 via the VXI data bus. It can only be accessed in the A32 address space. The base address of this memory is set by the VXI offset register, and it resides on a 1MByte boundary.

  • Page 18: Jtag Debugging Logic

    SMT301 User Guide Sundance 8 JTAG Debugging Logic This device is an SN74ACT8990 Test Bus Controller (TBC). It can only be accessed with a D16 cycle from the VXI host. The address range for access to this device is from the base address (specified in the VXI sub class offset register) to the base address + 0x7F.
  • Page 19 Sundance SMT301 User Guide Address Register Read/Write base + 02h JTAG Control 0 base + 06h JTAG Control 1 base + 0Ah JTAG Control 2 base + 0Eh JTAG Control 3 base + 12h JTAG Control 4 base + 16h JTAG Control 5 base + 1Ah JTAG Control 6...
  • Page 20 SMT301 User Guide Sundance (JTAG IN), or a TI debugger, then the TBC on this motherboard must be disabled. This is automatically done by a dedicated pin on the JTAG IN connector which forces the TDI signal for the first TIM site to be derived from this JTAG IN connector rather than the on board TBC.

  • Page 21: Comm-Port Interface

    Sundance SMT301 User Guide 9 Comm-port Interface This interface provides a route by which a VXI host can talk to a ‘C4x comm-port. Both D16 and D32 accesses are allowed. The following address / register map is used: Address Register Data Bits Read/Write base + 80h...

  • Page 22: Reset Board Register

    SMT301 User Guide Sundance 10 Reset Board Register This special control register is accessed in A32 space as either D16 or D32. When accessed as D16 it uses address base + C2h, and when using D32 at address base + C0h.

  • Page 23: C4X Memory Map

    Sundance SMT301 User Guide 11 ‘C4x Memory Map The C4x (TIM sites 1 or 5) have access to the Dual Port RAM, FIFO data register, general control register, general status register and VXI space. The addresses used are given in the table below: Address Resource Read/Write...

  • Page 24: Communications Ports

    SMT301 User Guide Sundance 12 Communications Ports The TMS320C4x processor has up to 6 byte-wide communications ports. In the case of the ‘C40, upon a reset 3 of these comm-ports are in output mode and the other 3 are in input mode. Similarly the 8 front-panel comm-port buffers are divided so that 4 reset to input and 4 reset to output.
  • Page 25 Sundance SMT301 User Guide 12.2 Front Panel Comm-Ports From the link patch headers, 8 comm-ports are taken to front panel mounted connectors via buffers, constructed from FCT245AT type devices with 64mA pull-down ability, and undershoot clamp diodes on all signals. All signals are pulled up to +3 volts with 100 ohm resistors.
  • Page 26 SMT301 User Guide Sundance Twisted pair Signal SHELL SHIELD The overall shield is clamped to the metal shell of the plug. RESET_OUT is an active low open collector output copied from the main board reset signal. -24- 10 April, 1997...

  • Page 27: Tim Sites

    Sundance SMT301 User Guide 13 TIM Sites There are 8 TIM sites numbered 1 to 8. Sites 1 and 5 have the optional global connector to allow TIM access to the DPR and FIFO. 13.1 TIM Connector Pin-Out The global connector contains the full ‘C4x global bus signals. For accesses by the ‘C4x to the global bus, the most significant address bit, A31 is a ‘1’.

  • Page 28: Fifo And High Speed Interface

    SMT301 User Guide Sundance 14 FIFO and High Speed Interface 14.1 High Speed Interface Control and Status A 32-bit port is provided that allows either global TIM site access to the Hewlett Packard Local Bus Interface: A high speed Hewlett Packard ECL ‘Local Bus’ interface is carried on the outer rows of P2, and is connected to a custom ECL interface device supplied by Hewlett Packard.
  • Page 29 Sundance SMT301 User Guide WIDTHIO1 WIDTHIO1 Drives WIDTHIO1when data is output CONT CONT, reset FLUSH FLUSH, reset INVEPACK INVEPACK, reset MODE0 MODE0, reset MODE1 MODE1, reset MODE2 MODE2, reset MODE3 MODE3, reset PACK PACK, reset PACKIN1 PACKIN1, reset PACKIN0, reset PACKIN0 STRIP STRIP, reset...

  • Page 30: Circuit / Schematic Description

    SMT301 User Guide Sundance 15 Circuit / Schematic Description 15.1 Schematic Sheet Titles Sheet Title Description Hewlett Packard Interface J2(VXIP2), ICI-5/10-17, R1-11/171-172 LED1-2 VXI Interface J1(VXIP1)/37(DIN30W0, IC18-31/218-219, R12-14/160 Static RAM J3-4, IC4x-47, R15-17/173-174 ‘C4x Link Interface C48-61,R18-27 Global TIM Site 1 J5, IC62-76, R28-44 Comms TIM Site 1 J6-7, IC77-92, R45-55...
  • Page 31 Sundance SMT301 User Guide The corresponding switch must be on for the address line to be decoded as 0. IC215 generates !VXIR1 which is fed to IC208 (ISPLSI1016-90LT). VXI AM0-4 are decoded in IC207 (GAL20V8C-5LJ), which generates !VXIR2 when the address modifiers are $29 (short non-privileged access) or $2D (short supervisory access).
  • Page 32 SMT301 User Guide Sundance Site Channels P and R are connected to the ‘C4x-VXI link interface. Channels X0-17 are buffered and fed to corresponding P0-17 link patch header channels. P18-23 are unbuffered front panel connected channels, which are also fed to the link patch header.
  • Page 33 Sundance SMT301 User Guide 15.7 Control Register Bit Descriptions The write only board control register is acessible to both the VXI bus and the TIMs. It is split into 4 separate registers: Control 1 15.7.1 Enables interrupt requests for TIM1 on IIOF1, located in IC202: Function FIFO IN empty FIFO IN almost empty...
  • Page 34 SMT301 User Guide Sundance FIFO OUT full VXI BERR Not defined Not defined 15.7.3 Control 3 Enables interrupt requests for VXI bus, located in IC202: Function FIFO IN empty FIFO IN almost empty FIFO IN almost full FIFO IN full FIFO OUT empty FIFO OUT almost empty FIFO OUT almost full...
  • Page 35 Sundance SMT301 User Guide VXI Bus request level bit 0 = DVBRS0 VXI Bus request level bit 1 = DVBRS1 Link Select VXI A1 during ‘C4x master cycle VXI LWORD during ‘C4x master cycle VXI AM0 during ‘C4x master cycle VXI AM1 during ‘C4x master cycle VXI AM2 during ‘C4x master cycle VXI AM3 during ‘C4x master cycle...
  • Page 36 SMT301 User Guide Sundance Function FIFO IN empty FIFO IN almost empty FIFO IN almost full FIFO IN full FIFO OUT empty FIFO OUT almost empty FIFO OUT almost full FIFO OUT full JTAG TIM1 IIOF0 TIM5 IIOF0 15.9 Link Status Register This read only register contains the ‘C4x link status bits: Function Receive data available...
  • Page 37 Sundance SMT301 User Guide VXI offset ‘C4x Address Peripheral C0000001 Control 2 Read/Write C0000002 Control 3 Read/Write C0000003 Control 4 Write C0000004 Status 1 Read Setting bit-4 of the Reset board register generates a continuous reset. 15.11 ‘C4x I/O Address Map ‘C4x I/O ‘C4x Address I/O Description...
  • Page 38 SMT301 User Guide Sundance address modifiers AM=$29 or $2D for VXI short address. address modifiers AM=$09 or $0D for VXI extended address. Selects a VXI interface reg, for D16 only transfers. Selects a Dual Port Ram location for D16/D32 transfers. Selects a board I/O register for D16/D32 transfers.
  • Page 39 Sundance SMT301 User Guide OFFSET x = $06 is $bbbb rw = Dual port ram offset (see above) SUBOFFS x = $08 is $cccc rw = Other regs offset (see above) SUBCLAS x = $1E is $1123 ro = Manuf sub class $1, Manuf $123 dddd = b15: rw A32 enable, cleared by board reset b14:...
  • Page 40 SMT301 User Guide Sundance CON3 z=$E8-EB VXI interrupt enables b0-10 CON4 z=EC-EF VXI bus master control b0-31 CONST z=$F0-F3 Interrupt flags b0-10 Note: con4.15 = linksel, 1 = TIM5, 0 = TIM1. 15.15 Link Control State Machines in IC60 The ‘Port Arbitration Unit’ (PAU) state machine is exactly as described in the TMS320C4x User’s Guide of 1993.
  • Page 41 Sundance SMT301 User Guide TIM Site TIM Port Patch Reset To Net Names Connector Connector CX17 CX16 CX15 CX14 CX13 CX12 CX10 15.17 Front Panel Connectors Layout There are 10 front panel connectors, which are arranged as follows when viewed from the front of the board: J35 and J34 are 20-way JTAG connectors.
  • Page 42 SMT301 User Guide Sundance Port Reset To Front Panel Patch Area 15.18.2 Front Panel Comm-port Cabling Connecting between ‘Reset to In’ and ‘Reset to Out’ ports requires a 1 to 1 cable: Cable plugs are: 3M Scotchflex 10126-6000EL FES part 038740A Plug shells are : 3M Scotchflex 10326-A200-00 FES part 038760D...
  • Page 43 Sundance SMT301 User Guide -CRDY -CREQ -CACK VCC1AMP -RESET SPARE The overall shield is attached to the body of the metal plug shell. The signal VCC1AMP is fused on the board at 1 amp. The fuse automatically resets when the load is removed. On ports which reset to input, pin 1 is always driven and pin 3 always received.
  • Page 44 SMT301 User Guide Sundance J34 Signal Direction Description JTAG Data In to SMT301 JTAG Data Out to SMT301 JTAG Test Mode Select JTAG Clock, 5MHz maximum JTAG Clock Return TCK_RET -TRST JTAG Reset -RESET SMT301 Board Reset Presence Detect, VCC (+5V) at 1 AMP fused -DETECT Detect external JTAG controller when GND CONFIG...
  • Page 45 Sundance SMT301 User Guide -TRST JTAG Reset -RESET SMT301 Board Reset Presence Detect WHEN PULLED HIGH -DETECT Signal external JTAG controller CONFIG OPEN COLL Global open collector C4x CONFIG EMU0 EMU0 in EMU1 EMU1 in SPARE1 SPARE2 10 April, 1997 -43-...

  • Page 46: Physical Characteristics

    SMT301 User Guide Sundance 16 Physical Characteristics 16.1 Power Consumption The static power consumption was measured under the following conditions: No TIMs fitted, no Front panel cables attached, the SMT301 is the only board fitted into a standard VXI rack. The empty rack backplane supply currents have been subtracted from the measured figures to obtain those given: Supply Voltage...
  • Page 47 Sundance SMT301 User Guide Specification Maximum Units Volts GND to Vee Volts -8.0 Volts Storage Temperature -65 to + 150 Celsius 16.5 Airflow Requirements The actual power consumption, airflow requirements and airflow resistance, are dependent on the TIMs fitted and on the activity on the board. The minimum total airflow provided should be the greater of the following (A or A.

  • Page 48: References

    SMT301 User Guide Sundance 17 References Texas Instruments TMS320c4x User’s Guide, 1993 Texas Instruments TIM-40 TMS320C4x Based Module, Specification 1993 VMEbus International Trade Association, VXIbus VMEbus Extensions for Instrumentation, System Specification v1.3, 1989 -46- 10 April, 1997...
  • Page 49 Sundance SMT301 User Guide 10 April, 1997 -47-...
  • Page 50 SMT301 User Guide Sundance -48- 10 April, 1997...
  • Page 51 Sundance SMT301 User Guide 10 April, 1997 -49-...
  • Page 52 SMT301 User Guide Sundance -50- 10 April, 1997...
  • Page 53 In line with our policy of continuous product development ™ reserves the right Sundance to alter these specifications without prior notice. All registered trademarks acknowledged. © No responsibility can be Sundance Multiprocessor Technology Limited, 1996. accepted for inaccuracies or omissions. Printed on re-cycled paper.
  • Page 54 SUNDANCE MU T G i i ed Chiltern House, Waterside Chesham HP5 1PS, United Kingdom Tel: +44 (0)1494 793167 Fax: +44 (0)1494 793168 email: sales@sundance.com http://www.sundance.com/...

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