LG RH4820W Service Manual page 83

Pin No. Pin Name
55 DGND -
56 MD13 3V
57 MD2 3V
58 MD12 3V
59 MD3 3V
60 DGND -
61 MD11 3V
62 MD4 3V
63 MD10 3V
64 MD5 3V
65 DVD33 -
66 DGND -
67 MD9 3V
68 MD6 3V
69 MD8 3V
70 MD7 3V
71 DVDD25 -
72 LDQM 3V
73 UDQM 3V
74 WE 3V
75 MCLK 3V
76 DVDD33 -
77 DGND -
78 CAS 3V
79 MCKE 3V
80 RAS 3V
81 MA9 3V
82 DVDD25 -
83 MBA 3V
84 MA8 3V
85 MA10 3V
86 MA7 3V
87 DVDD33 -
Type Description
- - Digital GND.(Buffer. Memory. Block)
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
- - Digital GND.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
- - Digital power.[3.3V](Buffer. Memory. Block)
- Digital GND.(Buffer. Memory. Block)
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
I/O Pull-up Buffer memory , Interface data bus.
- - Digital power.[2.5V]
O H Low byte, data input/output mask control signal.
O H High byte, data input/output mask control signal.
O H Buffer memory , Interface write enable signal.
O Pull-up SDRAM clock output.
- - Digital power.[3.3V](Buffer. Memory. Block)
- - Digital GND.(Buffer. Memory. Block)
O H Buffer memory , Interface column address strobe control signal.
O H SDRAM clock enable control signal.
O H Buffer memory , Interface row address strobe control signal.
O L Buffer memory , Interface address bus.
- - Digital power.[2.5V]
O L Buffer memory , Interface bank address signal.
O L Buffer memory , Interface data bus.
O L Buffer memory , Interface data bus.
O L Buffer memory , Interface data bus.
- - Digital power.[3.3V](Buffer. Memory. Block)
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