Kenwood NXR-700 Service Manual page 7

2. Receiver PLL circuits
The receiver unit (X55-309) has the 1st-PLL circuit for
controlling the VCO that generates the hetero signal to the
fi rst local oscillator, and the 2nd-PLL circuit for controlling
the VCO that generates the hetero signal to the second lo-
cal oscillator.
The 1st-PLL circuit consists of the VCO (Q7 and Q8), the
Buffer amplifi er (Q17), the RF amplifi ers (Q16 and Q3), the
PLL-IC (IC5), the Active loop filters (Q2 and Q4) and the
Band switches (Q14, Q10, Q11 and Q59). The signal in
the195.95 (K), 185.95 (K2) through under 209.95MHz (K),
194.95MHz (K2) band generated by VCO Q7 and the 209.95
(K), 194.95 (K2) through 223.95MHz (K), 203.95MHz (K2)
band generated by VCO Q8 is input to IC5 (pin5) via Q17
and Q16 as the Fin signal. The 6MHz reference signal gen-
erated by the DDS-IC (IC7) is input to IC5 (pin8) via Q3. Two
signals, Fin and REFin, are phase-compared as the 100kHz
comparison frequency by each frequency divider. The VCO
output with the frequency synchronized is input to the 1st-
+9V +9V
LPF
ATT
Q23 Q18
Q7
195.95~209.95MHz (K)
+9LV
185.95~
194.95MHz (K2)
+9V
Q10
SW
Div.
Q11
Q17 SW SW
Q8
209.95~223.95MHz (K)
+9LV
194.95~203.95MHz (K2)
+5V
+5V
LPF
5
1/N
Fin
Q16
IC5
CIRCUIT DESCRIPTION
16 IC30
IC6
ADC
Q14
+9LV
SW
Active
Q59
LPF
Q2,4
20 +5V
PD
LPF
8
1/R
REFin
Q3
Fig. 2 Receiver PLL circuits
Mixer as the first local oscillator Upper hetero signal ap-
proximately +17dBm via Q17, Q23, and Q18. The control
voltage is input to IC30 (ADC) pin16 via IC6.
Meanwhile, the 2nd-PLL circuit consists of the VCO (Q24),
the Buffer amplifi er (Q33), the RF amplifi er (Q38, Q22), and
the PLL-IC (IC11). The 99.0MHz signal generated by Q24 is
input to IC11 (pin5) as the Fin signal via Q38. The 19.2MHz
Internal reference clock distributed by the transmitter unit
(X56-311) is input as the REFin signal to IC11 (pin8) via Q22.
Two signals, Fin and REFin, are phase-compared by each
frequency divider as the comparison frequency of 200kHz.
The VCO output with the frequency synchronized is input to
IC9 (prescaler IC) pin2 via Q33 and Q21. The 49.5MHz sig-
nal is frequency-divided into halves by IC9 and is excited by
Q53 and distributed. One is input to IC12 (pin1) via Buffer
amplifi er_Q35. The other is input to IC13 (pin4) via Buffer
amplifi er_Q36. Both are input as approximately -16dBm for
the second local oscillator Lower hetero signal. The control
voltage at this point is input to IC30 (ADC) pin 10 via IC33.
+5V +3V +5V
2 7
IC9
ATT
1/2
Q21
49.5MHz
+9R
+9LV
LPF
Div.
Q24
Q33
99.0MHz
+5V
+5V
LPF
5
1/N PD
Fin
Q38
1/R
IC11
NXR-700
+5VA
ATT
Q35
LPF
Div.
Q53
+5VD
ATT
Q36
10 IC30
IC33
ADC
20
+5V
LPF
8
REFin
Q22
LPF
LPF
7