Main(Video) Schematic Diagram - JVC GR-D270US Schematic Diagrams

MAIN(VIDEO) SCHEMATIC DIAGRAM

0 1 MAIN(VIDEO)
TO PARAGON
DCO0
DCO1
DCO2
DCO3
DYO0
DYO1
DYO2
DYO3
OUTH
TO CPU,
OUTV
PARAGON
CLK27A
CLK27B
TO CPU
S2_DET
S_IN_L TL3203
VOI_IN
TO CPU,
VOI_OUT
OP DRV
VOI_CLK
VIF_CS
TO CPU,
CDS/TG, T_F_V_RST
OP DRV
VC0
VC1
VC2
VC3
BLKA
BLKB
BLKC
OSD_HD
TO CPU,
OSD_VD
PARAGON
DOT_CLK
PSCTL
ANA_IN_H TL3202
TO OP DRV
ASPECT
TO REG
REG_4.8V
REG_3.1V
REG_1.7V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-13(No.YF075)
R3206
0Ω
R3207
OPEN
C3206 0.01
R3730
4.7k
C3207 0.01
L3201
R3205
NQR0129-002X
OPEN
L3202
NQR0129-002X
T
C3201 C3202
10/6.3 1
HDCVF
VDCVF
TL3201
CSYNC
VDOUT
SCANMODE
VDD(C)
VSS
RESVD
RESHD
SDOUT
SDIN
SCLK
CS
VDD(I)
VSS
RST
C3203
1
SCANEN
AVDD
AVSS
VREF1
YSOUT
COMP1
ABAR1
IC3201
YCOUT
JCP8055FP
IREF1
AVSS
AVDD
COUT
VREF2
CBOUT
COMP2
ABAR2
R3208
820
C3208
0.01
C3209
0.01
L3203 L3204
NQR0006-001X 10u
T T
C3204 C3205
10/6.3 10/6.3
R320
27k
(N