Pcie-Dio96H Block Diagram - MC PCIe-DIO96H User Manual

PCIe-DIO96H User's Guide

PCIe-DIO96H block diagram

PCIe-DIO96H functions are illustrated in the block diagram shown here.
5V Power
Spare
+5V (VDD)
Molex
Fuse
Connector
Fuse
+5V
Protection
Fuse
+5V
Protection
High Drive FOURTHPORT
FOURTHPORTA
FOURTHPORTB
24
FOURTHPORTCL
FOURTHPORTCH
High Drive THIRDPORT
THIRDPORTA
THIRDPORTB
24
THIRDPORTCL
THIRDPORTCH
High Drive SECONDPORT
SECONDPORTA
SECONDPORT B
24
SECONDPORT CL
SECONDPORT CH
High Drive FIRSTPORT
FIRSTPORTA
FIRSTPORTB
24
FIRSTPORTCL
FIRSTPORTCH
10 k
EEPROM
Pull Resistor
Switch
12
Network
Note: Port CL and CH
are tied together on
the pull resistors.
To +5V components
(Note: Outputs to CPLD
are 3.3V with 5V inputs)
BP1
In
8
Out
8
BP2
In
8
Out
8
Control
Bus
Programmable
Logic Device
BP3
In
8
Out
8
Logic, Control,
Decode/Status
BP4 BP(1:4)
In
8 96
Out
8 8
5V (VDD)
8
GND
Figure 1. PCIe-DIO96H functional block diagram
1.5V
Regulator
5V Detect
Software Sensing
Complex,
PCI-to-Local
Bus
Timing
(CPLD)
3.3V, 32-bit, 33 MHz
LAD(0:7)
Interface
8
Local
Address
&
Data Bus
9
Introducing the PCIe-DIO96H
3.3V 3.3V
3.3V Board Power
PCIe-to-PCI
x1 Link
Bridge
PCI Bus
Bus
BADR2
Boot
+
EEPROM
BADR3