Post Codes - Acer Aspire ZE8 Series Service Manual

Post Codes

These tables describe the Post Codes and components of the POST process.
Sec:
NO_EVICTION_MODE_DEBUG EQU
0x MTRR setup
C2
0x Enable cache
C3
0x Establish cache tags
C4
0x Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0.
C5
0xCF Cache Init Finished
Memory:
DEBUG_BIOS EQU 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC)
0x First memory check point
A0
0x Enable MCHBAR
01
0x Check for DRAM initialization interrupt and reset fail
02
0x Verify all DIMMs are DDR or DDR2 and unbuffered
03
0x Detect an improper warm reset and handle
04
0x Detect if ECC SO-DIMMs are present in the system
05
0x Verify all DIMMs are single or double sided and not asymmetric
06
0x Verify all DIMMs are x8 or x16 width
07
0x Find a common CAS latency between the DIMMS and the MCH
08
0x Determine the memory frequency and CAS latency to program
09
0x Determine the smallest common TRAS for all DIMMs
10
0x Determine the smallest common TRP for all DIMMs
11
0x Determine the smallest common TRCD for all DIMMs
12
0x Determine the smallest refresh period for all DIMMs
13
Chapter 4
1 (CommonPlatform\sec\Ia32\SecCore.inc)
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