Pioneer VSX-74TXVi Service Manual page 267

5
No. Pin Name I/O
21 P10 I Video pixel input port
22 P9 O Video pixel output port
23 P8 O Video pixel output port
24 P27 I/O Video pixel input/output port
25 P7 O Video pixel output port
26 P6 O Video pixel output port
27 P5 O Video pixel output port
28 P4 O Video pixel output port
29 P26 I/O Video pixel input/output port
30 P25 I/O Video pixel input/output port
31 P24 I/O Video pixel input/output port
32 P23 I/O Video pixel input/output port
33 P22 I/O Video pixel input/output port
34 P21 I Video pixel input port
35 DCLK_IN I Clock input signal
36 LLC1 O Line-locked output clock for the pixel data output
37 XTAL1 O 27MHz crystal connect pin
38 XTAL I Input pin for 27MHz crystal
−
39 DVDD Digital core supply voltage (1.8V)
−
40 DGND Digital ground
41 P3 O Video pixel output port
42 P2 O Video pixel output port
43 P1 I Video pixel input port
44 P0 I Video pixel input port
45 P20 I Video pixel input port
The recommend external loop filter must
46 ELPF O
be connected to this pin
−
47 PVDD PLL supply voltage (1.8V)
−
48 PVDD PLL supply voltage (1.8V)
−
49 AGND Analog ground
−
50 AGND Analog ground
−
51 AGND Analog ground
52 SOG I Sync on green input
53 AIN7 I Analog video input channel
54 AIN1 I Analog video input channel
55 AIN8 I Analog video input channel
56 AIN2 I Analog video input channel
57 AIN9 I Analog video input channel
58 AIN3 I Analog video input channel
−
59 NC No connect pin
−
60 AGND Analog ground
5
6
Function No. Pin Name
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSX-74TXVi
6
7
I/O
CAPY1 I ADC capacitor network
CAPY2 I ADC capacitor network
−
AVDD Analog supply voltage (3.3V)
REFOUT O Internal voltage reference output
CML O Common-mode level pin for the internal ADCs
−
AGND Analog ground
BIAS O External bias setting
CAPC1 I ADC capacitor network
CAPC2 I ADC capacitor network
−
AGND Analog ground
AIN10 I Analog video input channel
AIN4 I Analog video input channel
AIN11 I Analog video input channel
AIN5 I Analog video input channel
AIN12 I Analog video input channel
AIN6 I Analog video input channel
SOY I Sync on luma input
RESET I System reset input
DE_IN I Data enable input signal
Selects the I2C address for the
ALSB I
ADV7400A control and VBI readback port
SDA1 I/O I2C port serial data input/output
SCLK1 I I2C port serial clock input (max 400kHz)
P40 I Video pixel input port
P39 I Video pixel input port
VS_IN I VS input signal
Can be configured in CP mode to be
either a digital HS input signal or a digital
HS_IN/CS_IN I
CS input signal used to extract timing in
5-wire or 4-wire RGB mode.
P38 I Video pixel input port
P37 I Video pixel input port
−
DGND Digital ground
−
DVDD Digital core supply voltage (1.8V)
P19 O Video pixel output port
P18 O Video pixel output port
P17 O Video pixel output port
P16 O Video pixel output port
P36 I Video pixel input port
P35 I Video pixel input port
P34 I Video pixel input port
FIELD/DE O Field sync signal output/data enable
VS O Vertical sync output signal
P33 I Video pixel input port
7
8
A
Function
B
C
D
E
F
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