Cpu-6803; Reset Circuit; Rom; Cassette Interface - Radio Shack TRS-80 Service Manual

CPU-6803

The main component of this microcomputer
system is the 6803 CPU. This is a 40-pin in-
tegrated circuit which provides the address,
data, and miscellaneous control signals. The
CPU receives the main clock frequency of
3.579545 MHz from the modulator assembly
and divides this by 4 to produce an operating
frequency of 0.89 MHz. This frequency is avail-
able as the processor clock E.
This processor chip is designed to be used in a
minimum hardware configuration so, I/O lines
are provided directly from the CPU chip. In the
MC-10 computer these I/O lines are used to
address the keyboard and to support the cas-
sette and RS232 interface.
The 6803 CPU is able to support several differ-
ent modes of operation. For the MC-10 the CPU
is operating in mode 2. The CPU mode is
selected at power-up by the state of lines P20,
P21, and P22. P20 and P22 are connected by a
diode to Reset so that during power-up these
lines are low. P21 is connected to a pull-up
resistor so that during power-up it is high.
Mode 2 operates with 128 bytes of internal
RAM, a full 16 line address bus and an 8 bit
data bus which is multiplexed with the lower
eight address lines. Due to the multiplexed
address and data bus, two external devices are
required. A 74LS373 is used to latch the
address lines. This occurs during the low por-
tion of the E clock when the CPU is not access-
ing external devices. The latch signal (AS) is
provided by the CPU. The other external device
is a 74LS245. This bi-directional buffer is
required to isolate the RAM output lines, which
are providing data to the video display genera-
tor during the low portion of the E clock, away
from the CPU data bus. This buffer is controlled
by the device selection logic.

RESET CIRCUIT

The reset circuit is composed of switch S1
diode D9, resistor R24, capacitor C8, and two
gates of IC U12. R24 and C8 form a simple time
constant so that during power up or whenever
the reset switch is pressed, the reset line will
stay low for a few milliseconds before returning
to the high state. The reset input to the 6803
does not provide hysteresis so the reset signal
must be buffered by U12 before being con-
nected to the CPU. The final component of the
circuit is diode D9 which is provided to allow
for rapid cycling of the power switch.

ROM

The MC-10 uses a single 8K x 8 ROM to store
the BASIC operating language. This is located
in a 16K memory map segment between hex
C000 - FFFF. This device is connected directly
to the multiplexed address/data, however any
possible contention is avoided by enabling the
ROM only during the high cycle of the E clock.

CASSETTE INTERFACE

The cassette interface is composed of an out-
put attenuator connected to a CPU output line
and an input zero crossing detector. Most of
the important cassette parameters are con-
trolled by software. However, there is no cas-
sette motor relay in the Micro Color Computer
and cassette recorder operation must be man-
ual.
The cassette format chosen uses a sinewave of
2400 or 1200 Hertz to yield a Baud rate of ap-
proximately 1500 Baud. In this format, a 0 (or
logic low) is represented by one cycle of 1200
Hertz. A 1 (or logic high) is represented by one
cycle of 2400 Hertz. A sample of data is shown
in Figure 2. A typical program tape would con-
sist of a leader of alternating 1's and 0's, fol-
lowed by one or more blocks of data. A block of
data is composed of 0 to 255 bytes of data with
a checksum, sync byte, and the block length.
The output circuit utilizes a CPU output line to
produce a sinewave of 1200 or 2400 Baud. This
signal is then attenuated to approximately 1
volt and connected to the auxiliary input of the
cassette recorder.
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