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CyberResearch CYDIO 96P User Manual

Multi-channel digital i/o board 96-channel, ttl-level pci board with 100-pin connection
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®
Digital I/O
C
DIO 96P
Y
Multi-Channel Digital I/O Board
96-Channel, TTL-Level PCI Board
with 100-Pin Connection
USER'S MANUAL
VER. 2 • NOV 2000
&
No part of this manual may be reproduced without permission.
CyberResearch
, Inc.
®
www.cyberresearch.com
25 Business Park Dr., Branford, CT 06405 USA
203-483-8815 (9am to 5pm EST) FAX: 203-483-9024

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  • Page 1 100-Pin Connection USER’S MANUAL VER. 2 • NOV 2000 & No part of this manual may be reproduced without permission. CyberResearch , Inc. ® www.cyberresearch.com 25 Business Park Dr., Branford, CT 06405 USA 203-483-8815 (9am to 5pm EST) FAX: 203-483-9024...
  • Page 3 CyberResearch, Inc. In no event will CyberResearch, Inc. be liable for direct, indirect, special, incidental, or consequential damages arising out of the use of or inability to use the product or documentation, even if advised of the possibility of such damages.

  • Page 5: Table Of Contents

    TABLE OF CONTENTS 1 INTRODUCTION ..........2 INSTALLATION .
  • Page 6 This page is blank.

  • Page 7: Introduction

    1 INTRODUCTION The CyDIO 96P is a 96-bit line digital I/O board. The board provides the 96 bits in four 24-bit groups. Each group provides an 8-bit port A and port B, as well as an 8-bit port C that can be split into independent 4-bit port C-HI and a 4-bit port C-LO.
  • Page 8 This page is blank.

  • Page 9: Installation

    2 INSTALLATION The CyDIO 96P boards are completely plug-and-play. There are no switches or jumpers on the board. All board addresses are set by your computer’s plug-and-play software. InstaCal is the installation, calibration and test software supplied with your data acquisition / IO hardware.
  • Page 10 This page is blank.

  • Page 11: O Connections

    3 I/O Connections 3.1 CABLES AND SCREW TERMINAL BOARDS The board has a 100-pin, high-density Robinson-Nugent male connector (Figure 3-1). A CBL 100xx cable is used to split the 100 I/O lines into two, 50-wire cables. One connector has pins 1 to 50, the other has 51 to 100. The two I/O connectors can be connected directly to two screw-terminal boards such as the CYSTP 50E, STA 100, STA 50H or CYSTP 502E.

  • Page 12: Connector Diagram

    3.2 CONNECTOR DIAGRAM The CyDIO 96P I/O connector is a 100-pin type connector accessible from the rear of the PC at the expansion backplate See Figure 3-1 below for the board pin out. Port A7 B Port A7 D Port A6 B...
  • Page 13 BOARD’S CBL 100xx 100-PIN I/O CABLE CONNECTOR I/O PINS 1 TO 50 SIGNAL CONDITIONING or 50-PIN SCREW TERMINAL BOARD. I/O PINS 51 TO 100 SIGNAL CONDITIONING OR 50-PIN SCREW TERMINAL BOARD Figure 3-2. Cable CBL 100xx Configuration...
  • Page 14 Port A7 D Port A6 D Port A5 D Port A4 D Port A3 D Port A2 D Port A1 D Port A0 D Port B7 D Port B6 D Port A6 D 2 Port A7 D Port B5 D Port A4 D Port A5 D Port B4 D...

  • Page 15: Signal Connection Considerations

    3.3 SIGNAL CONNECTION CONSIDERATIONS All the digital inputs on the CyDIO 96P are 8255 CMOS TTL. The CyDIO 96P output signals are 8255 CMOS. CyberResearch, Inc. offers a wide variety of digital signal conditioning products that provide an ideal interface between high voltage and/or high current signals and the CyDIO 96P.

  • Page 16: Cyerb 24 & Cyssr 24 Connections

    3.4 CYERB 24 & CYSSR 24 CONNECTIONS CyDIO 96P boards provide digital I/O in two major groups of 48 bits each (96 total, but each side of the CBL 100xx cable provides 48 bits). However, many popular relay and SSR boards provide only 24-bits of I/O. The CYERB 24 and CYSSR 24 each implements a connector scheme where all 96 bits of the CyDIO 96P board may be used to control relays and/or SSRs.

  • Page 17: Software

    Most packaged application programs, such as SoftWIRE, DAS Wizard and HP-VEE have drivers for the CyDIO 96P. If the package you own does not appear to have drivers for the boards, please fax or e-mail the package name and the revision number from the install disks.
  • Page 18 This page is blank.

  • Page 19: Register Maps

    5 REGISTER MAPS The PCI Controller, a PLX-9052, has four configuration, control, and status registers (Table 5-1). They are described in the following section. Table 5-1. I/O Region Register Operations I/O Region Function Operations BADR0 PCI memory-mapped configuration 32-bit double word registers BADR1 PCI I/O-mapped config.

  • Page 20: Badr2

    INTE Interrupt enable (local): 0 = disabled, 1 = enabled (default) INTPOL Interrupt polarity: 0 = active low (default), 1 = active high Interrupt status: 0 = interrupt not active, 1 = interrupt active PCINT PCI interrupt enable: 0 = disabled (default), 1 = enabled LEVEL/EDGE Interrupt trigger control: 0 = level triggered mode (default), 1 = edge triggered mode...

  • Page 21: Badr3

    5.4 BADR3 BADR3 is an 8-bit data bus for reading, writing and control of the individual 82C55 chips and the 82C54. Refer to Table 5-2 for register offsets. Table 5-2. BADR3 Registers REGISTER READ FUNCTION WRITE FUNCTION BADR3 + 0 Group 0 Port A Data Group 0 Port A Data BADR3 + 1...
  • Page 22 GROUP 0, PORT B DATA BADR3 + 1 READ/WRITE GROUP 0, PORT C DATA BADR3 + 2 READ/WRITE GROUP 0 CONFIGURE BADR3 + 3 READ/WRITE This register is used to configure the Group 0 ports as either input or output, and configures the operating mode to mode 0, 1 or 2.

  • Page 23: Group 1 8255 Configuration & Data

    Table 5-3. DIO Port Configurations/Per Group Programming Codes Values Notes: ‘CU’ is PORT C upper nibble, ‘CL’ is PORT C lower nibble. 5.4.2 Group 1 8255 Configuration & Data GROUP 1, PORT A DATA BADR3 + 4 READ/WRITE GROUP 1, PORT B DATA BADR3 + 5 READ/WRITE GROUP 1, PORT C DATA...

  • Page 24: Group 2 8255 Configuration & Data

    GROUP 1 CONFIGURE BADR3 + 7 READ/WRITE 5.4.3 Group 2 8255 Configuration & Data GROUP 2, PORT A DATA BADR3 + 8 READ/WRITE GROUP 2, PORT B DATA BADR3 + 9 READ/WRITE GROUP 2, PORT C DATA BADR3 + A hex READ/WRITE GROUP 2 CONFIGURE BADR3 + B hex...

  • Page 25: 8254 Configuration & Data

    GROUP 3, PORT B DATA BADR3 + D hex READ/WRITE GROUP 3, PORT C DATA BADR3 + E hex READ/WRITE GROUP 3 CONFIGURE BADR3 + F hex READ/WRITE 5.4.5 8254 Configuration & Data COUNTER 1 DATA BADR3 + 10 hex READ/WRITE The 82C54 counters 1 and 2 have been configured in hardware to produce a 32-bit counter for use in interrupt generation.

  • Page 26: 8255 Interrupt Source Configure

    COUNTER CONFIGURATION BADR3 + 13 hex READ/WRITE This register is used to set the operating modes of each of the 82C54’s counters. Configure the counters by writing mode information to the Configure register, followed by the count information written to the specific counter (data) registers. Refer to the Celeritous 82C54 data sheets for more detailed information.

  • Page 27: Counter Interrupt Source Configure

    5.4.7 Counter Interrupt Source Configure BADR3 + 15 hex READ/WRITE INTEN CTRIR CTR1 INTEN Enables or disabled interrupts. 1 = enabled, 0 = disabled CTRIR Enables or disables the counters as an interrupt source. 1 = counters may generate interrupts. 0 = counters cannot generate interrupts. CTR1 Controls whether counter 2 is the interrupt source, or counter 1 is the interrupt source.
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  • Page 29: Specifications

    6 SPECIFICATIONS Power Consumption 150 mA max Digital Input / Output Digital Type Four 82C55 Number of I/O • Configuration per 82C55 2 banks of 8 and 2 banks of 4, or • 3 banks of 8, or 2 banks of 8 with handshake 3.0 volts min @ −2.5mA Output High Output Low...

  • Page 30: Crystal Oscillator

    Interrupts The interrupt control registers function with the four 82C55 devices and the 82C54 counter timer to provide interrupt sources. Interrupt INTA# - mapped to IRQn via PCI BIOS at boot-time PCI Interrupt enable Programmable through PLX9052 INTCSR Interrupt polarity High or low level.

  • Page 31: Electronics And Interfacing

    7 ELECTRONICS AND INTERFACING This brief introduction to the electronics most often needed by digital I/O board users covers a few key concepts. IMPORTANT NOTE WHENEVER AN 82C55 IS POWERED-ON OR RESET, ALL PINS ARE SET TO HIGH-IMPEDANCE INPUT. FOLLOWING STANDARD TTL FUNCTIONALITY, THESE INPUTS WILL TYPICALLY FLOAT HIGH, AND MAY HAVE ENOUGH DRIVE CURRENT TO TURN ON EXTERNAL DEVICES.

  • Page 32: Ttl To Solid State Relays

    The SIP may be installed as pull-up or pull-down. At each location, PORT#A, B & C on the CyDIO 96P series boards, there are 10 holes in a line. One end of the line is +5V, the other end is GND. They are marked HI and LO respectively. The eight holes in the middle are connected to the eight lines of a port 1 through 4, A, B, or C.

  • Page 33: Voltage Dividers

    The most convenient way to use solid state relays and a CyDIO 96P board is to use a Solid State Relay Rack. An SSR Rack is a circuit board with input buffer amplifiers that are powerful enough to switch the SSRs. The buffer amplifiers and SSRs are socketed.
  • Page 34 0 volts when off and 24 volts when on, you cannot connect that directly to the CyDIO 96P digital inputs. The voltage must be dropped to 5 volts max when on. The Attenuation is 24:5 or 4.8. Use the equation above to find an appropriate R1 if R2 is 1K.
  • Page 35 EC Declaration of Conformity We, the manufacturer, declare under sole responsibility that the product: CyDIO 96P Digital I/O board Part Number Description to which this declaration relates, meets the essential requirements, is in conformity with, and CE marking has been applied according to the relevant EC Directives listed...
  • Page 36 For Your Notes...

  • Page 37: Product Service

    Signal connections and programming are the two most common sources of difficulty. CyberResearch support personnel can help you solve these problems, especially if you are prepared for the call.
  • Page 38 CyberResearch, Inc. will, at its option, repair or replace the defective item under the terms of this warranty, subject to the provisions and specific exclusions listed herein.

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