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Convergence Panel
Phase-Locked Loop:
The phase-locked loop produces a 13.59mhz signal, which is phase locked to the 15,734 Hz
horizontal blanking pulse (HBLN).
(Figure 12)
This signal is used as the system clock which is
used by the Convergence Spline Processor (CSP) and the three digital to analog converters
(dacs). In this manner, the convergence correction waveforms are synchronized to the
deflection system of the television set.
Transistors Q10, and related components make up the oscillator. Adjustable coil L3 is used to
set the free run frequency oscillator which is at the middle range when the dc voltage at TP3 is
1.5 volts.
Convergence Spline Processor (CSP)
When the TV set is turned On, IC300 the main microprocessor on the Small Signal Board
reads the data stored in IC11 on the Convergence Board via the I2C bus. This information
contains the x-y coordinates for the 35 alignment points of each color visible on the screen
during convergence set up along with other register settings used by the CSP.
The CSP uses fourth order polynomial equations called quadric splines in the algorithm to
convert the data of the 35(7 horizontal by 5 vertical) alignment points into 24 points per
horizontal line by 243 vertical lines. The resulting digital data is supplied to IC365, IC165, and
IC265, the three two channel dacs, which convert the digital data into analog convergence
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