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PCIe-SIO4BX2
User's Manual
Four Channel PCIe High Performance Serial I/O
Featuring RS422/RS485/RS232 Software Configurable Transceivers
and 32K Byte FIFO Buffers (256K Byte total)
RS-485
RS-422/V.11
RS-232/V.28
General Standards Corporation
8302A Whitesburg Drive
Huntsville, AL 35802
Phone: (256) 880-8787
Fax: (256) 880-8788
URL:
www.generalstandards.com
E-mail:
techsupport@generalstandards.com
Revision NR
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Summary of Contents for General Standards Corporation PCIe-SIO4BX2
- Page 1 Four Channel PCIe High Performance Serial I/O Featuring RS422/RS485/RS232 Software Configurable Transceivers and 32K Byte FIFO Buffers (256K Byte total) RS-485 RS-422/V.11 RS-232/V.28 General Standards Corporation 8302A Whitesburg Drive Huntsville, AL 35802 Phone: (256) 880-8787 Fax: (256) 880-8788 URL: www.generalstandards.com E-mail: techsupport@generalstandards.com...
- Page 2 General Standards Corporation does not assume any liability arising out of the application or use of any product or circuit described herein, nor is any license conveyed under any patent right of any rights of others.
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Page 3: Related Publications
RELATED PUBLICATIONS ZILOG Z16C30 USC® User’s Manual ZILOG Z16C30 USC® Product Specifications Databook ZILOG, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 (408) 370-8000 http://www.zilog.com/ PLX PCI 9056 Data Book PLX Technology Inc. 390 Potrero Avenue Sunnyvale, CA 4085 (408) 774-3735 http://www.plxtech.com/ EIA-422-A –... -
Page 4: Table Of Contents
TABLE OF CONTENTS CHAPTER 1: INTRODUCTION ..........................1 ..........................1 ENERAL ESCRIPTION Z16C30 U ....................2 NIVERSAL ERIAL ONTROLLER FIFO ........................2 RANSMIT ECEIVE ........................3 ULTIPROTOCOL RANSCEIVERS PMC/PCI I ............................. 3 NTERFACE IO ........................... 3 ENERAL URPOSE ..........................3 ONNECTOR NTERFACE .............................. - Page 5 ......................... 20 OARD VS HANNEL EGISTERS ................. 21 ROGRAMMABLE SCILLATOR ROGRAMMABLE LOCKS ............................... 21 LOCK ETUP ....................23 ULTIPROTOCOL RANSCEIVER ONTROL DCE/DTE M ............................23 ............................23 OOPBACK ODES IO ..........................24 ENERAL URPOSE 3.10 ..............................24 NTERRUPTS 3.11 PCI DMA ..............................24 CHAPTER 4: PCI INTERFACE ..........................
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Page 6: Chapter 1: Introduction
CHAPTER 1: INTRODUCTION General Description The PCIe-SIO4BX2 is a four channel serial interface card which provides high speed, full-duplex, multi-protocol serial capability for PCIe applications. The PCIe-SIO4BX2 combines multi-protocol Dual Universal Serial Controllers, deep external FIFOs, and software selectable multi-protocol transceivers to provide four fully independent synchronous/asynchronous serial channels. -
Page 7: Z16C30 Universal Serial Controller
Figure 1-1 Block Diagram of PCIe-SIO4BX2 Z16C30 Universal Serial Controller The PCIe-SIO4BX2 is designed around the Z16C30 Universal Serial Controller( USC). The Z16C30 is a dual channel multi-protocol serial controller which may be software configured to satisfy a wide variety of serial communications applications. -
Page 8: Multiprotocol Transceivers
General Standards will also work with customers to fabricate custom cables. Consult factory for details on custom cables. New Features The PCIe-SIO4BX2 has been enhanced with several new features. These include improved receive data status recording, timestamping of data, flexible FIFO memory allocation, sync/standard channel select, and channel reset. Rev NR... -
Page 9: Chapter 2: Local Space Registers
CHAPTER 2: LOCAL SPACE REGISTERS Register Map The SIO4BX2 is accessed through three sets of registers – PCI Registers, USC Registers, and GSC Firmware Registers. The GSC Firmware Registers and USC Registers are referred to as Local Space Registers and are described below. -
Page 10: Firmware Revision : Local Offset X 0000
0x003C Read/Write Ch 3 Control/Status 0000CC00 0x0040 Read/Write Ch 4 Tx Almost Full/Empty 00070007 0x0044 Read/Write Ch 4 Rx Almost Full/Empty 00070007 0x0048 Read/Write Ch 4 Data FIFO 000000XX 0x004C Read/Write Ch 4 Control/Status 0000CC00 0x0050 Read/Write Ch 1 Sync Byte 00000000 0x0054 Read/Write... -
Page 11: Board Control : Local Offset X 0004
2.1.2 Board Control: Local Offset 0x0004 The Board Control Register defines the general control functions for the board. Board Reset 1 = Reset all Local Registers and FIFOs to their default values Notes: This bit will automatically clear to 0 following the board reset. Board Reset will NOT reset programmable oscillator. -
Page 12: Board Status : Local Offset X 0008
2.1.3 Board Status: Local Offset 0x0008 The Board Status Register gives general overall status for a board. The Board Jumpers (D1:D0) are physical jumpers which can be used to distinguish between boards if multiple SIO4 boards are present in a system. D31:9 RESERVED 0 = Standard... -
Page 13: Hannel Rx Almost Lags Ocal Ffset 0044
2.1.6 Channel RX Almost Flags: Local Offset 0x0014 / 0x0024 / 0x0034 / 0x0044 Defines the Almost Full and Almost Empty Flags for the Tx FIFO. The Almost Full/Empty Flags are status bits in the Channel Control/Status Register, and are edge-triggered interrupt sources to the Interrupt Registers. D31:16 RX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted... -
Page 14: Hannel Ync Etect Yte Ocal Ffset 005C
D7:0 Channel Control Bits 1 = Reset USC ((Pulsed - will automatically clear to ‘0’) Notes: Following a USC Reset, the next access to the USC must be a write of 0x00 to Local Offset 0x100 (Ch1/2) or Local Offset 0x300 (Ch3/4). ... -
Page 15: Interrupt Control : Local Offset X 0060
IRQ14 Channel 4 Rx FIFO Almost Full Rising Edge Falling Edge IRQ15 Channel 4 USC Interrupt Level Hi NONE IRQ16 Channel 1 Tx FIFO Empty Rising Edge Falling Edge IRQ17 Channel 1 Tx FIFO Full Rising Edge Falling Edge IRQ18 Channel 1 Rx FIFO Empty Rising Edge Falling Edge... -
Page 16: Interrupt Edge /Level : Local Offset X 0068
Likewise, if a level interrupt is enabled and the interrupt source is true, the interrupt status will be reasserted immediately after clearing the interrupt, and an additional interrupt will be requested. 2.1.13 Interrupt Edge/Level: Local Offset 0x0068 The Interrupt Edge Register is an information only (read only) register. This register can be used by a generic driver to determine if the interrupt source is edge or level triggered. - Page 17 DCE/DTE Mode When DCE/DTE Mode is enabled (Bit D31=1), this bit set the mode to DCE (1) or DTE (0). DCE/DTE mode changes the direction of the signals at the IO Connector. D27:24 Transceiver Protocol Mode Transceiver Mode RS-422 / RS-485 RESERVED RS-232 RESERVED...
- Page 18 D14:13 Cable RTS Output Source Output Source Notes USC_CTS field (D10:D9) must equal ‘11’ USC_CTS Output RTS Output Rx FIFO Almost Full ‘0’ Drive low ‘1’ Drive Hi D12:11 USC_DCD Direction Setup If DCD is used as GPIO, set this field to ‘00’ and set Pin Source Register D16:D15 for output / Pin Status Register D3 for input.
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Page 19: Hannel In Tatus Ocal Ffset 009C
D5:3 USC_RxC Source The clock source must agree with the USC Clock setup (USC I/O Control Reg D5:3) to ensure the signal is not being driven by both the USC and the FPGA. USC_RxC Source USC IOCR D2:D0 Setup Prog Clock 000 (Input) Inverted Prog Clock 000 (Input) -
Page 20: Xac
This register allows boards to change functionality on each channel. Currently, a channel can only be defined as Standard or Sync. For SIO4BX-Sync information, please refer to the PCIe-SIO4BX2-SYNC manual. Channel 4 FW Type –> 01 = Standard / 04 = Sync D31:D24 Channel 3 FW Type –>... -
Page 21: Features Register : Local Offset X 00Fc (0 X 00197Af4)
2.1.17 Features Register: Local Offset 0x00FC (0x00197AF4) The Features Register allows software to account for added features in the firmware versions. Bits will be assigned as new features are added. See Appendix B for more details. D31:21 RESERVED 1 = No Rx Status byte (std only) D19:D18 10 = Internal Timestamp (std only) D17:D16... -
Page 22: 8-Bit Usc Register Access
Since the USC Reset physically resets the USC, the first access to the USC following the reset must reinitialize the BCR in the USC. To complete the Reset process, the user should write data 0x00 to USC base address offset 0x100 or 0x300 to correctly initialize the BCR. -
Page 23: Usc Register Memory Map
2.2.4 USC Register Memory Map To access the USC in 8-bit mode, the driver is required to access the upper and lower bytes of each register independently. The odd address byte will access the upper byte of each register (D15-D8), and the even address byte will access the lower byte (D7-D0). -
Page 24: Chapter 3: Programming
CHAPTER 3: PROGRAMMING Introduction This section addresses common programming questions when developing an application for the SIO4. General Standards has developed software libraries to simplify application development. These libraries handle many of the low-level issues described below, including Resets, FIFO programming, and DMA. These libraries may default the board to a “standard”... -
Page 25: Fifo Counters
3.2.3 FIFO Size Unlike previous SIO4 boards which had ordering options for different FIFO sizes, the PCIe-SIO4BX2 always uses 32k byte deep FIFOs. Board vs. Channel Registers Since four serial channels are implemented on a single board, some registers apply to the entire board, while others are unique to each channel. -
Page 26: Programmable Oscillator / Programmable Clocks
Programmable Oscillator / Programmable Clocks Four On-Board Programmable Oscillators provide each channel with a unique programmable clock source. In order to program the oscillator, it is necessary to calculate and program values for different clock frequencies. General Standards has developed routines to calculate the necessary values for a given setup and program the clock generator. - Page 27 FPGA CLOCK CONTROL ProgClk TxAuxC Source TxAuxC Pin Source Reg D18:D17 RxAuxC / RxAuxC TxAuxC Connector RxAuxC On-Board TxC Source Programmable ProgClk Oscillator Pin Source Reg D8:D6 USC TxC Source Pin Source Reg D2:D0 USC TxC USC TxC USC RxC Source USC RxC USC RxC...
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Page 28: Multiprotocol Transceiver Control
cable RxC in the Pin Source Register. Since the FPGA will source both USC clocks, they must be programmed as inputs in the USC I/O Control Register. The preceding suggestions should work for most applications. The default Pin Source Register value should set the clocks to work with both scenarios –... -
Page 29: General Purpose Io
location for the transmit signals (TxC, TXD, RTS), and the receive signals will use these same signals as the receive inputs. Since signals are transmitted and received through the transceivers, this mode allows the setup to be verified (including signal polarity) without any external connections. Since external signals could interfere with loopback operation, all cables should be disconnected when running in external loopback mode. - Page 30 data, the transfer will complete with invalid results. This is the preferred mode for DMA operation. The FIFO Counters may be used to determine how much space is available for DMA so that the FIFO will never over/under run. Demand Mode DMA requires less software control, but runs the risk of losing data due to an incomplete transfer.
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Page 31: Chapter 4: Pci Interface
Since many features of the PCI9056 are not utilized in this design, it is beyond the scope of this document to duplicate the PCI9056 User’s Manual. Only those features, which will clarify areas specific to the PCIe-SIO4BX2 are detailed here. Please refer to the PCI9056 User’s Manual (See Related Publications) for more detailed information. -
Page 32: Local Configuration Registers
4.1.2 Local Configuration Registers The Local Configuration registers give information on the Local side implementation. These include the required memory size. The SIO4BX2 memory size is initialized to 4k Bytes. All other Local Registers initialize to the default values described in the PCI9056 Manual. 4.1.3 Runtime Registers The Runtime registers consist of mailbox registers, doorbell registers, and a general-purpose control register. -
Page 33: Chapter 5: Hardware Configuration
CHAPTER 5: HARDWARE CONFIGURATION Board Layout The following figure is a drawing of the physical components of the PCIe-SIO4BX2: FPGA PCIe Bridge RP10 Figure 5-1: Board Layout – Top Board ID Jumper J2 Jumper J2 allows the user to set the Board ID in the Board Status Register (See Section 2.1.3). This is useful to uniquely identify a board if more than one SIO4BX2 card is in a system. -
Page 34: Termination Resistors
Termination Resistors The PCIe-SIO4BX2 transceivers have built in termination resistors for the RS-422/RS485 mode. The built in RS- 422/RS485 termination is a 120 Ohm parallel termination. If desired, the internal termination resistors may be disabled by setting bit D30 in the Pin Source Register. -
Page 35: Interface Connector
Interface Connector User I/O Connector: 68-pin SCSI connector (female) (P2) Part Number: AMP/TYCO 787170-7 Mating Connector: AMP/TYCO 749111-6 (or equivalent) Pin 34 Pin 1 Pin 68 Pin 35 Note: RS422/RS485 mode or RS232 mode is set on a per channel basis RS422/RS485 RS232 RS422/RS485... -
Page 36: Chapter 6: Ordering Options
C to +85 Interface Cable General Standards Corporation can provide an interface cable for the SIO4BX2 board. This standard cable is a twisted pair cable for increased noise immunity. Several standard cable lengths are offered, or the cable length can be custom ordered to the user’s needs. -
Page 37: Appendix A: Programmable Oscillator Programming
APPENDIX A: PROGRAMMABLE OSCILLATOR PROGRAMMING The 4 on-baord clock frequencies are supplies via two Cypress Semiconductor CY22393 Programmable Clock Generatosr. In order to change the clock frequencies, this chip must be reprogrammed. This document supplies the information necessary to reprogram the on-board clock frequencies. GSC has developed routines to calculate and program the on-board oscillator for a given set of frequencies, so it should not be necessary for the user need the following information –... - Page 38 Measure Channel 4 Clock Reserved (Unused) Status Word Readback Control 0 => Status Word D31-D8 == Measured Channel Value 1 => Status Word D31-D8 == Control Word D23-D0 Post-divider set 0 = Ignore D23-D8 during Command Word Write 1 = Set Channel Post-Dividers from D23-D8 during Command Word Write D11-D8 Channel 1 Post-Divider D15-D12...
- Page 39 The Internal RAM is defined as follows: RAM Address 0x08–0x57 correspond directly to the CY22393 registers. Address Description Default Value 0x00 – 0x05 Reserved (Unused) 0x00 0x06 Reserved 0xD2 0x07 Reserved 0x08 0x08 ClkA Divisor (Setup0) 0x01 0x09 ClkA Divisor (Setup1) 0x01 0x0A ClkB Divisor (Setup0)
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Page 40: Appendix B: Firmware Revisions / Features Register
Firmware Register - Local Offset 0x00 (0xE5100100) D31:16 HW Board Rev 0xE510 PCIe-SIO4BX2 Rev NR 1 = Features Register Present 1 = Complies with this standard 1 = 66MHz PCI bus interface... - Page 41 Feature Register - Local Offset 0xFC (0x00197AF4) D31:D21 Unused 1 - Rx Status byte inserted in FIFO D19:D18 Timestamp 01 = single external clock 10 = single internal clock D17:D16 FPGA Reprogram field 01 = Present 00 = Not Present D15:D14 Configurable FIFO space 01 - Rx/Tx select.
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