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1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CA1 and A PART OF CA2 CIRCUIT
DESCRIPTIONS
Around CCD block
1. IC Configuration
CA1 board
IC901 (ICX274AQ) CCD imager
CA2 board
IC901 (H driver, CDS, AGC and A/D converter)
2. IC901 (CA1) (CCD imager)
[Structure]
Interline type CCD image sensor
Image size
Pixels in total
Recording pixels
Pin No.
Symbol
Vø
1
4
2
Vø
3A
3
Vø
3B
4
Vø
3C
5
Vø
2A
6
Vø
2B
7
Vø
2C
8
Vø
1
9
GND
10
V
OUT
3. IC904 (V Driver) and IC901 (CA2 board) (H driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD.
IC904 are V driver. In addition the XV1-XV4 signals which are
output from IC102 are the vertical transfer clocks, and the
XSG signal which is output from IC102 is superimposed onto
XV2 and XV3 at IC902 in order to generate a ternary pulse.
In addition, the XSUB signal which is output from IC102 is
used as the sweep pulse for the electronic shutter. A H driver
is inside IC901 (CA2 board), and H1A, H1B, H2A, H2B and
RG clock are generated at IC901 (CA2 board).
4. IC901 (CA2 board)
(CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(29) of IC901 (CA2 board). There are inside the sampling hold
block, AGC block and A/D converter block.
The setting of sampling phase and AGC amplifier is carried
out by serial data at Pin (37) of IC911. The video signal is
carried out A/D converter, and is output by 10-bit.
Diagonal 8.293 mm (1/1.8 type)
1688 (H) x 1248 (V)
1600 (H) x 1200 (V)
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
Table 1-1. CCD Pin Description
10
8
7
9
11
12
13
14
Fig. 1-1. CCD Block Diagram
Pin No.
Symbol
11
V
DD
øRG
12
13
Hø
2B
Hø
14
1B
GND
15
øSUB
16
C
17
SUB
18
V
L
19
Hø
1A
20
Hø
2A
CDS
CCDIN
CLAMP
RG
HORIZONTAL
4
DRIVERS
H1-H4
Fig. 1-2. IC901 Block Diagram
– 2 –
6
5
4
3
2
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
G
R
B
G
B
G
G
R
G
R
Horizontal register
15
16
17
18
19
(Note) :
Photo sensor
Pin Description
Circuit power
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
Substrate clock
Substrate bias
Protection transistor bias
Horizontal register transfer clock
Horizontal register transfer clock
VRT
VRB
VREF
2~36 dB
12
PxGA
VGA
ADC
CLAMP
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
INTERNAL
GENERATOR
REGISTERS
SL
SCK
HD
VD
SDATA
1
(Note)
20
DOUT
CLPOB
CLPDM
PBLK
CLI
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