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DSC-P200
For Schematic Diagram
• Refer to page 4-42 for printed wiring board.
1
2
CH-146 BOARD
A
CCD SIGNAL PROCESS
XX MARK:NO MOUNT
Note: CH-146 board (CP101) is included
in SY-123 complete board.
B
C
CL024
D
D2
C020
0.01u
CL025
D3
CL026
D4
CL020
V6
CL027
D5
CL007
V1
E
VHLD
CL028
CL019
D6
CL008
VST
CL029
D7
CL010
V3B
CL030
F
D8
CL021
VSUB
V3A
CL031
CL011
D9
CL059
DLLSL
C010
CL032
0.1u
D10
G
CL033
D11
CL071
RGVDD
CL034
D12
CL035
D13
CL005
RG
H
CL053
FE
I
CL052
TG3V
CL054
CL055
HVDD
CL056
DRV3V
J
05
4-9
3
4
5
6
: Voltage measurment of the CSP ICs
R010
R011
XX
XX
and the Transistors with
not possible.
C018
0.1u
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
NC
D2
RST
D3
VMM
D4
Vhld
VDD4
D5
V1A
Vst
D6
V1B
VHH
D7
VLL
IC101
V3A
D8
CCD SIGNAL PROCESSOR,
SUB
TIMING GENERATOR
IC101
V3B
CXD3436GA-T4
D9
DLLSL
SY-123 (1/9)
AVD1
CP101
D10
PAGE 4-12
of LEVEL3
SNCSL
Note: The number from CL001 to CL074 on
SSGSL
CH-146 board corresponds to the pin
number of CP101 on SY-123 board.
D11
AVD2
TEST1
D12
VSS1
D13
RG
NC
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
R003 100
C013
0.1u
C012
0.1u
C024
0.1u
7
8
9
mark, are
TG_GND
FE_GND
C006
0.1u
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
NC(LME)
VR
C023
R008
XX
100
AVSS2
FB001
MCKO
NC(LMO)
C004
C004
C004
XX
XX
XX
VSS8
C005
AVD8
0.1u
VDDA1
OSCI
CKO
L(LP2E)
C019
OSCO
0.1u
VDD3
CCD_GND(LP2O)
C026
PBLK
0.1u
VSS7
C027
0.1u
CCDIN
TEST3
CKI
C002
NC
0.01u
TEST2
AVSA/B
C017 XX
C017 XX
C017 XX
NC(L)
AVDA/ B
C009 0.1u
P38
C001
XX
NC(LP1E)
CLPOB
R005
P50
XX
VDDD
C011 0.1u
P6
C016 XX
NC(LP1O)
DLLRST
R002 XX
AVSS1
NC
R006 XX
R001
C025
0.1u
XX
4-10
10
11
CL064
CL062
CL061
CL060
GND
CL068
CL067
CL066
CL065
GND
CL069
CL073
CL072
CL070
GND
CL048
MCK TG
CL063
CCD_GND
CL006
CCD_IN
CL047
TG_CLK
CL058
AVSA
CL057
AVDA
CH-146

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