Pentium 82430 VX/P54C User's Manual & Technical Reference page 28

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DRAM RAS to CAS
Delay
DRAM Read Burst
Timing
DRAM Write Burst
Timing
Fast MA to RAS# Delay
CLK
Fast EDO Path Select
Refresh RAS# Assertion Use the default setting.
ISA Bus clock
System BIOS Cacheable Disabled Ð The ROM area F0000H-
Video BIOS Cacheable
8Bit I/O Recovery Time
16Bit I/O Recovery
Time
Memory Hole At 15M-
16M
Use the default setting.
Use the default setting.
Use the default setting.
Use the default setting.
Use the default setting.
Use BIOS default setting or choose:
/4 Ð for 60, 66 MHz CPU Bus Frequency
/3 Ð for 50, 55 MHz CPU Bus Frequency.
FFFFFH is not cached.
Enabled Ð The ROM area F0000H-
FFFFFH is cacheable if cache
controller is enabled.
Disabled Ð The video BIOS C0000H-
C7FFFH is not cached.
Enabled Ð The video BIOS C0000H-
C7FFFH is cacheable if cache
controller is enabled.
Use the default setting.
Use the default setting.
Choose Enabled or Disabled (default).
Some interface cards will map their ROM
address to this area. If this occurs, you
should select Enabled, otherwise use
Disabled.
BIOS Setup