Sony D-NE300 Service Manual page 20

D-NE300/NE300CK/NE301/NE301CK/NE306CK
Q Q
3 7 6 3 1 5 1 5 0
• IC Block Diagrams
– MAIN Board –
IC301 AN75315A
BST BST PW MT MT
BIAS BEEP
OUT SW BIAS SW SW TC
IN IN
24 21 20 19 18 17
23 22
BIAS BEEP
PW MT
SW SW OUT B OUT A
ADD
B
BST
ADD
A
PW
PW PW
C
B A
PWC
SW
7
1 2 3 4 5 6 8
VCC
BST ADD RF IN PWC OUT B OUT C OUT A
NF OUT SW
IC403 TB2138AFG
60 59 58 57 56 55 54 53 52
VREF
DC IN 61 DC IN
T E
L 1 3 9 4 2 2 9 6 5 1 3
62
REGB
LEVEL
DET 63 CONTROLLER
SHIFTER
IMM1 64
CONTROL
BAND GAP
CHGB 65
CHARGE
REF
66 VIN
VMMNT_O
STANDBY
REF
CHGMNT_O 67
68
BATM1_I
BATM2_I 69
BRK 70
71
PREGND
PWM 72
APWM 73
FG 74
DTC2 75
76
DTC3
77
WI
LOGIC/
78
VI
MOTOR DRIVER
w w w
79 VCPU
UI
VG
COM 80
PRE DRIVER
1 2 3 4 5 6 7 8
ATT
GND IN B IN A SW
16 15 14 13
ALC ALC
ATT
SW
ALC
DET
11
9 10 12
PWR MIX ALC ALC
GND OUT IN DET
51 50 49 48 47 46 45 44 43 42 41
CH1 CH2 CH3
H BRIDGE H BRIDGE H BRIDGE
VCPU
BIAS
CLX & OSC
SAW
GEN
VREF VCC0
IVREF
x a o
VG
VCC3
. i
9 10 11 12 13 14 15 16 17 18 19 20
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IC701 CXR710160-207R
64 63 62 61 60 59 58 57 56 55
LRCKI
1
BCKI 2
3
VDIOCD0
PCMDI 4
5
DVDD4
6
TAPTD0
7
SCANEN
8
DVDD0
DVSS0 9
10
DVIO0
11
VDIOCD1
12
PF4/XRDE
13
PI3/BCKO
PI2/LRCKO 14
PI0/PCMDO 15
16
EVA
Q Q
40 LATCH
3 7 6
39 DATA
38 CLOCK
37 WAKEUP
36 LD
35 RSTOUT
34 SYNC
33 PREGND
PD
32
PWG
31
30 INM2
29 RF2
28 PWS
27 INP2
26 VREF
25 STNG
17 18 19 20 21 22 23 24 25 26
24 SEP
23 SEM
u 1 6 3
y SEO
22
21 GSW
20 20
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2 4
8 9 9
54 53 52 51 50 49
DAC
INTERFACE
CD-ROM
INTERFACE
INTERRUPT CONTROLLER
DMAC (CH3) DMAC (CH1)
EEPROM SERIAL
3 INTERFACE 1 5 1 5 0 8 9 2
DMAC (CH0)
DMAC (CH2)
WATCHDOG
TIMER
CLOCK GENERATOR/
PRESCALLER/ SYSTEM CONTROLLER
TIME BASETIMER
MAGIC GATE
CORE
RAM
160K BYTES
RAM
512K BYTES
27 28 29 30
m
c o
.
2
8 9 9
48 PE3/RxD1
47 PE2/TxD1
46 PE1/RxD0
45 PE0/TxD0
44 DVSS2
43 DVDD2
42 PC3/SCS0
41 PC2/SI0
40 PC1/SO0
39
VDIOCD2
38 PC0/SCK0
37 PF3/T3
36 PF2/EC2/INT4
4 9 8 2 9 9
35
PF1/T1
34 PF0/EC0/INT3
33 NRST
HUFFMAN HW
VIRTUAL ENGINE
CORE
ARM77TDMI
CPU CORE
31 32