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Figure 1. NCV7425EVB
Getting Started
Master/Slave Configuration
The NCV7425 evaluation board can be configured as
Master or Slave node. Furthermore, Master node LIN bus
pull-up resistance (R
) can be tied to VBB supply line or
LIN
to INH pin (See the figures below).
VBB
INH
NCV7425
R
LIN
LIN Bus
LIN
C
LIN
Figure 2. Master with Pull-up to VBB
Basic Connection
A simple LIN network configuration is shown in the
figure below. One Master and one Slave node is required
(Master/Slave Configuration).
VBAT
LIN
GND
MASTER Node
GND
MCU
VCC
NCV7425EVB
VBB
VBB
LIN Bus
Figure 3. Master with Pull-up to INH
MASTER
Figure 5. NCV7425 Evaluation Setup Connection
http://onsemi.com
NCV7425 PIN CONNECTIONS
V
BB
LIN
GND
GND
WAKE
INH
OTP_SUP
N.C.
The EMC immunity of the Master-node device can be
further enhanced by adding a capacitor between the LIN
output and ground (C
capacitor is determined by the length and capacitance of the
LIN bus, the number and capacitance of Slave devices, the
pull-up resistance of all devices (Master and Slave), and the
required time constant of the system.
VBB
INH
NCV7425
R
LIN
LIN
C
LIN
SLAVE Node
GND
MCU
VCC
2
16
1
V
2
15
RxD
14
3
TxD
4
13
RSTN
5
12
STB
11
6
EN
7
10
TEST
8
9
N.C.
SOIC−16 LEAD
WIDE BODY
EXPOSED PAD
CASE 751AG
). The optimum value of this
LIN
VBB
LIN Bus
C
LIN
Figure 4. Slave Configuration
CC
VBB
INH
NCV7425
LIN
SLAVE
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