1. Manuals
  2. Brands
  3. Zephyr Manuals
  4. Receiver
  5. UDPSDR-HF2
  6. User manual

Zephyr UDPSDR-HF2 User Manual

Front-end
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
UDPSDR-HF2 Receiver Front-end
User's Manual
Version 3.5 – 3 October 2013
© Copyright 2013 Zephyr Engineering, Inc

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the UDPSDR-HF2 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Zephyr UDPSDR-HF2

Summary of Contents for Zephyr UDPSDR-HF2

  • Page 1 UDPSDR-HF2 Receiver Front-end User’s Manual Version 3.5 – 3 October 2013 © Copyright 2013 Zephyr Engineering, Inc...
  • Page 2 ETWORK CABLE NOT PLUGGED IN NCORRECT NETWORK ADDRESS ASSIGNMENTS DLL NOT IN CORRECT DIRECTORY THEORY OF OPERATION UDPSDR-HF2 F RONT ARDWARE UPDSDR-HF2 FPGA C SPECIFICATIONS APPENDIX A – UDPSDR-HF2 J1/J2 PIN DEFINITIONS UDPSDR-HF2 User’s Manual Version 3.5 – 3 October 2013...

  • Page 3: Hardware Description

    The following sections will help familiarize you with the setup and connections to your SDRstick HF2 SDR receiver. 1.1 UDPSDR-HF2 Connectors, Headers and Jumpers See Figure 1 for UDPSDR-HF2 connector and jumper locations. P1- OPT Power In J3- Power In J6- Phones Out J5- RF Input J1 –...
  • Page 4 © Copyright 2013 Zephyr Engineering, Inc Note that the HF2 uses the BeMicroSDK pin assignments, not the MEC connector pin assignments from the Samtec data sheet. Pin 1 is marked on HF2 by a white dot. The pin 1 ends of J1 and J2 are closest to the JP1 header. The BeMicroSDK pin 1 is clearly marked with a “1”.
  • Page 5 © Copyright 2013 Zephyr Engineering, Inc Center Pin +5VDC@950mA GND - Pin 2 +5VDC - Pin 1 2.35mm x 0.70mm Figure 3 - Power Connector Detail 1.1.1.3 J4 – Reference Clock Input (optional) J4 can be used as an optional reference clock input. You may apply a 2V peak-to-peak 10MHz sine-wave input from a GPS-disciplined oscillator to this standard SMA jack.
  • Page 6 © Copyright 2013 Zephyr Engineering, Inc 1.1.2.2 P3 and P4 – Optional Filter Headers Optional headers P3 and P4 can be used to replace FL1 with a daughter card containing user-defined mixing, filtering and/or amplification. The user must remove R21 and R22 and install headers at P3 and P4 (Molex part #87759-0664, Digi-Key part #0877590674-ND).
  • Page 7 PC or network switch. 1.2.1.3 MEC Edge connector (X701) The 80-contact MEC-style edge connector plugs into the UDPSDR-HF2 front-end board. All of the digital signals between the HF2 and the BeMicroSDK use this connector.
  • Page 8 FIFO overflow (internal error condition) LED6 LED5 LED4 LED3 LED2 Heartbeat: flashes ~ 1Hz from HF2 122.88MHz clock LED1 (bottom) Heartbeat: flashes ~ 1Hz from BeMicroSDK 50MHz clock Table 2- UDPSDR-HF2 Firmware User LED Indicators UDPSDR-HF2 User’s Manual Version 3.5 – 3 October 2013...
  • Page 9 © Copyright 2013 Zephyr Engineering, Inc LED8 – ADC Overload LED7 – Internal FIFO Overflow LED6 – not used LED5 – not used LED4 – not used LED3 – not used LED2 – UDPSDR-HF2 Clock Heartbeat LED1 – BeMicroSDK Clock Heartbeat Figure 6- BeMicroSDK User LEDs 1.2.3 BeMicroSDK Switches...
  • Page 10 © Copyright 2013 Zephyr Engineering, Inc S504 – not used S503 – FPGA Reset S502 - Reconfiguration SW1-2 not used SW1-1 not used Figure 7 - BeMicroSDK Switches 1.2.3.2 Slide Switches (SW1-1, SW1-2) The two slide switches, SW1-1 (bottom) and SW1-2 (top), can be read under FPGA firmware control.

  • Page 11: Detailed Operation

    © Copyright 2013 Zephyr Engineering, Inc 2 Quick Start Guide This quick start guide will lead you through the steps to get your SDRstick receiver operating. Please refer to Section 3 for in-depth information on each of these steps. If your BeMicroSDK came pre-programmed from the factory, you can skip steps QS1 and QS3.
  • Page 12 © Copyright 2013 Zephyr Engineering, Inc  Install applications  Check system information and update hardware drivers  Enable/disable both wired and wireless network ports  Change PC IP address and network mask  Enable and disable PC DHCP client ...
  • Page 13 © Copyright 2013 Zephyr Engineering, Inc the FPGA configuration SRAM can be overwritten with a new firmware load from the USB port at any time.) For the SDRstick HF2 receiver to work immediately on power-up, the BeMicroSDK configuration flash ROM must be programmed with the FPGA firmware load.
  • Page 14 © Copyright 2013 Zephyr Engineering, Inc <svn.sdrstick.com>. Sections 2.4 and 2.5 of the lab walk you through the Quartus II Web Edition and USB Blaster driver installation. 3.1.2.1 Quartus II Web Edition This is an extremely large download (about 4.4GB). Unless you have a fast connection to the Internet, it will take a long time to download.
  • Page 15 © Copyright 2013 Zephyr Engineering, Inc NOTE: The USB Blaster driver is not available as a separate download. If you intend to power your SDRstick from the USB port, you must download and install either the Quartus II Web Edition or the Quartus II Programmer software.
  • Page 16 © Copyright 2013 Zephyr Engineering, Inc 3.3.2 QS3a – Creating a User Flash Block File When SDRstick Programmer is opened, the Create UFB pane contains a default MAC address of 00:07:ed:fc:fd:fe, a default IP address of 192.168.1.26 and the DHCP client turned off.
  • Page 17 10Mbps Ethernet has insufficient bandwidth to support this receiver.) 3.4.3 QS4d – Power Connect the power supply to J3. The BeMicroSDK and UDPSDR-HF2 combination requires about 950mA at 5VDC to operate properly. While the recommended way to supply power is through connector J3, you may also supply power through the USB connector if the USB port will supply enough power.
  • Page 18 © Copyright 2013 Zephyr Engineering, Inc USB 3.0 ports should be able to supply enough current, and some USB 2.0 ports (especially on powered hubs) have been known to work, even though the required current is above the maximum USB 2.0 limit.
  • Page 19 © Copyright 2013 Zephyr Engineering, Inc buttons above the date display. HDSDR saves the setting of Mute from run to run, so if you had the receiver muted when you shut HDSDR down, it will still be muted when you launch HDSDR again.
  • Page 20 © Copyright 2013 Zephyr Engineering, Inc There is currently no way to control the 31-dB front-end step attenuator from SDR#. Eventually it will be supported through the SDRSTICK GUI, invoked by clicking the Configure button in the SDR# top menu bar.

  • Page 21: Troubleshooting

    © Copyright 2013 Zephyr Engineering, Inc Readme.txt file to install the GNURadio SDRstickTM sourceblock and an example GRC flowgraph. The contents of the Readme.txt file are reproduced in Figure 9 for your convenience. - Uncompress in directory of your choice.

  • Page 22: Theory Of Operation

    . Place a copy in the same directory as the executable file is located. 5 Theory of Operation The next two sections describe the design of the UDPSDR-HF2 in very basic terms. 5.1 UDPSDR-HF2 Front-End Hardware The UDPSDR-HF2 PCB block diagram is shown in Figure 10. The signal flow is straightforward, with the RF signal passing through the step attenuator, LPF, LNA and anti-alias filter before being sampled by the ADC.
  • Page 23 Figure 10 - UDPSDR-HF2 Hardware Block Diagram 5.2 UPDSDR-HF2 FPGA Code The UDPSDR-HF2 simplified FPGA block diagram is shown in Figure 11. This very basic flow shows the Numerically Controlled Oscillator and the two multipliers that serve as a down-converter, followed by two decimating filters. The I/Q data is buffered by a FIFO and sent to the Ethernet MAC for transmission as UDP packets on the network.

  • Page 24: Specifications

     MDS: -128dBm @ 14MHz (500Hz BW) for 3dB noise floor increase  Antenna connection: standard SMA  Power consumption: +5VDC @ 950mA (including BeMicroSDK)  Dimensions, UDPSDR-HF2: 56mm x 80mm (2.2”W x 3.3”L)  Dimensions, including BeMicroSDK: 56mm x 200mm (2.2”W x 8.0”L) UDPSDR-HF2 User’s Manual...

  • Page 25: Appendix A - Udpsdr-Hf2 J1/J2 Pin Definitions

    © Copyright 2013 Zephyr Engineering, Inc 7 Appendix A – UDPSDR-HF2 J1/J2 Pin Definitions J1/J2 Pin Signal Name J1/J2 Pin Signal Name 3.3V (not used) 3.3V (not used) 122_88MHz EXT_OSC_10MHZ ADC_CLKA INA0 INA1 INA2 INA3 INA4 INA5 INA6 INA7 INA8...
  • Page 26 © Copyright 2013 Zephyr Engineering, Inc 3.3V – not used by HF2 122_88MHz – 3.3V buffered 122.88MHz clock output or hi-Z (see DRV_CLK_OUT_N) EXT_OSC_10MHZ – buffered, squared 10MHz clock output from J4 reference clock ADC_CLKA – LTC2208 CLKOUTA (buffered clock) output pin GND –...

Table of Contents