Sanyo VPC-X360E Service Manual page 3

3. IC902 (H Driver) and IC904 (V Driver)
An H driver (IC902) and V driver (IC904) are necessary in
order to generate the clocks (vertical transfer clock, horizon-
tal transfer clock and electronic shutter clock) which driver
the CCD.
IC902 is an inverter IC which drives the horizontal CCDs (H1
and H2). In addition the XV1-XV4 signals which are output
from Pins (166), (167), (169) and (171) of IC102 are the ver-
tical transfer clocks, and the XSG1 and XSG2 signals which
is output from Pins (168) and (170) of IC102 is superimposed
onto XV1 and XV3 at IC904 in order to generate a ternary
pulse. In addition, the XSUB signal which is output from Pin
(165) of IC102 is used as the sweep pulse for the electronic
shutter, and the RG signal which is output from Pin (159) of
IC102 is the reset gate clock.
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
Fig. 1-2. IC902 Block Diagram
CPP3
1
Change Pump
VH
2
DCIN
3
XSHT
4
XV2
5
XV1
6
XSG1
7
XV3
8
XSG2
9
XV4
10
Fig. 1-3. IC904 Block Diagram
14 V
CC
13 6A
12 6Y
11 5A
10
5Y
4A
9
8 4Y
CPP1
20
19
CPP2
DC OUT
18
VSHT
17
16
V
L
V
2
15
V
1
14
V 13
M
V
3
12
V
4
11
4. IC905 (CDS, AGC Circuit and A/D converter)
The video signal which is output from the CCD is input to
Pins (26) and (27) of IC905. There are S/H blocks inside IC905
generated from the XSHP and XSHD pulses, and it is here
that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102 of the CA2 circuit
board. The gain of the AGC amplifier is controlled by the volt-
age at pin (29) which is output from IC102 of the CA2 circuit
board and smoothed by the PWM.
PBLK CLPDM PGACONT1 PGACONT2 SHP SHD ADCCLK
19 23 29
CLAMP
PGA
27
PIN
CDS
26
DIN
36
ADCIN
REFERENCE
37 48 47
18
CMLEVEL VRT VTB STBY CLPOB ADCMODE
Fig. 1-4. IC905 Block Diagram
30 22
21 16
TIMING
GENERATOR
10
2
A/D
MUX S/H
11
12
CLAMP
AD9802
17
20 41 33
43
ACVDD ADVDD
DOUT
DRVDD
DVDD