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Code
Beeps
0Ah
0Bh
0Ch
0Eh
0Fh
10h
11h
12h
13h
14h
16h
1-2-2-3
17h
18h
8254
1Ah
8237
1Ch
20h
1-3-1-1
22h
1-3-1-3
24h
26h
28h
29h
2Ah
2Ch
1-3-4-1
2Eh
1-3-4-3
2Fh
30h
1-4-1-1
32h
33h
36h
38h
3Ah
3Ch
3Dh
42h
45h
46h
2-1-2-3
48h
49h
4Ah
4Bh
4Ch
4Eh
50h
Chapter 4
POST Routine Description
Initialize CPU registers
Enable CPU cache
Initialize caches to initial POST values
Initialize I/O component
Initialize the local bus IDE
Initialize Power Management
Load alternate registers with initial POST values
Restore CPU control word during warm boot
Initialize PCI Bus Mastering devices
Initialize keyboard controller
BIOS ROM checksum
Initialize cache before memory autosize
timer initialization
DMA controller initialization
Reset Programmable Interrupt Controller
Test DRAM refresh
Test 8742 Keyboard Controller
Set ES segment register to 4 GB
Enable A20 line
Autosize DRAM
Initialize POST Memory Manager
Clear 512 KB base RAM
RAM failure on address line xxxx*
RAM failure on data bits xxxx* of low byte of memory bus
Enable cache before system BIOS shadow
RAM failure on data bits xxxx* of high byte of memory bus
Test CPU bus-clock frequency
Initialize Phoenix Dispatch Manager
Warm start shut down
Shadow system BIOS ROM
Autosize cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Display CPU type and speed
145
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