Ic Block Diagram & Description - Sanyo MCD-ZX300 Service Manual

IC BLOCK DIAGRAM & DESCRIPTION
IC901 TC94A23FN503 (CD PROCESSOR)
X 77
SS
XI 76
XO 78
XV 80
DD
DV 81
SR
RO 82
83
DV
RR
DV 84
DD
DV 85
RL
LO 86
DV 87
SL
V 46,75
DD
V 47,76
SS
MXO 93
X'tal
OSC
MXI 94
P1-3 24
Port 1
P1-0 21
SBSY
Interrupt
92
INTR
Serial
Interface
P4-3(SCK/SCL) 32
P4-2(S10/S11/SDA) 31
Port 4
P4-1(S12) 30
29
P4-0(ADin/BUZR)
BUZR
P3-3(ADin3) 28
27
P3-2(ADin2)
Port 3
P3-1(ADin1) 26
P3-0 25
74 73 72 71 70 69
Clock
gene.
PWM
CD clock
ZDET
SERVO
control
ROM
Digital equalizer
Automatic adjustment
RAM
P2-0~P2-3
IN1
MPX
CPU clock
Timer
Data Reg(16 bit)
Cont.
ROM
(16 x 8192 Step)
Program
Counter
AD
Stack Reg.
Conv.
(8Level)
Bias
ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF
97 98 99 100
68 67 66 65 64 63 62 61
DA
V
REF
AD
V
REF
CLV
circuit
servo
Sub code decoder
Audio out Digital out
CD Reset
Reset
Micon interface
SBSY
CLCK, DATA, SFSY,
LRCK, BCK, MBOV, IPF
G-Reg.
RAM
(4 x 512 word)
Instruction
Decoder
LCD Driver/Output Port
1 2 10 11 12 13 14
- 8 -
60 59 58 55
V
REF
Data
slicer
PLL
TMAX
VCO
Synchronous
guarantee EFM
decode
16k SRAM
Correction circuit
OT19-22
R/W Buf.
ALU
F/F
Reset
Power on Reset
Port 8
15 16 17 18
57 RFI
56 SLCO
50 TMAX
49 PDO
48 P2V
REF
54 VCOF
53 PV
REF
51 LPFO
50 LPFN
45 SBOK
44 SBSY
43 DOUT
42 OT22(COFS)
41 OT21(SPDA)
40 OT20(SPCK)
39 OT19(HSO)
91 HOLD
88 TESTM
38 TESTC
37 IN1(BCKin)
IN2
89
33 P2-0(EMPHin)
34 P2-1(HSO in)
P2-2(LRCKin)
35
36 P2-3(DATAin)
90 RST
19,96 MV
DD
20,95 MV
SS