HP dx7300 Technical Reference Manual page 70

System Support
The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.
DMA Controller Registers
Table 4-11 lists the DMA Controller Registers and their I/O port addresses. Note that there is a
set of registers for each DMA controller.
Register
Status
Command
Mode
Write Single Mask Bit
Write All Mask Bits
Software DRQx Request
Base and Current Address—Ch 0
Current Address—Ch 0
Base and Current Word Count—Ch 0
Current Word Count—Ch 0
Base and Current Address—Ch 1
Current Address—Ch 1
Base and Current Word Count—Ch 1
Current Word Count—Ch 1
Base and Current Address—Ch 2
Current Address—Ch 2
Base and Current Word Count—Ch 2
Current Word Count—Ch 2
Base and Current Address—Ch 3
Current Address—Ch 3
Base and Current Word Count—Ch 3
Current Word Count—Ch 3
Temporary (Command)
Reset Pointer Flip-Flop (Command)
Master Reset (Command)
Reset Mask Register (Command)
4-18
Table 4-1 1.
DMA Controller Registers
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Controller 1 Controller 2
008h 0D0h
008h 0D0h
00Bh 0D6h
00Ah 0D4h
00Fh 0DEh
009h 0D2h
000h 0C0h
000h 0C0h
001h 0C2h
001h 0C2h
002h 0C4h
002h 0C4h
003h 0C6h
003h 0C6h
004h 0C8h
004h 0C8h
005h 0CAh
005h 0CAh
006h 0CCh
006h 0CCh
007h 0CEh
007h 0CEh
00Dh 0DAh
00Ch 0D8h
00Dh 0DAh
00Eh 0DCh
Technical Reference Guide
R/W
R
W
W
W
W
W
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
R
W
W
W