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2.2
I²C bus
•
The I²C bus is a two bus system consisting of a data line and a clock line.
•
5V is set for SDA / SCL. [Fig 2.0]
•
Allow a large number of switching and control functions of GP-31 chassis.
The UOC IC601 generates bus signals which control the following hardware
configuration.
1. EEPROM IC1103
These memories are 1K-byte, non-volatile memories of microchips, and bit pattern of
1024 x 8 bits.
2. Tuner TU001
To select a desired channel signal from the several RF signal from TV stations and
convert the selected RF signal into a signal of an intermediate frequency (IF).
3. Sound Processor IC2101
The sound processor IC will cover the sound processing of all analog TV-Standards
worldwide, as well as the NICAM digital sound standards.
2.3
Memory IC
Fig 2.0
Fig 2.1
9
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