Pin No.
Pin Name
101
VSS1
102
VDD0
103
AVSS
104
AVDD
105
PLLCK
106
XPLLEN
107
TST
108
LRCT
109
LROUT
110
BKOUT
111
VSS2
112
VDD1
113
BCK0
114
BCK1
115
LRCK0
116
LRCK1
117 to 120
SIA to SID
I/O
—
Ground terminal
—
Power supply terminal (+3.3V)
—
Ground terminal
—
Power supply terminal (+3.3V)
I/O
PLL output/test clock signal input terminal
I
PLL cell oscillation enable signal input terminal
I
Test data input terminal
I
Frequency counter input terminal
O
Clock driver signal output terminal
O
Clock driver signal output terminal
—
Ground terminal
—
Power supply terminal (+3.3V)
I
BCK input
I
BCK input
I
LRCK input
I
LRCK input
—
Serial data input
Description
75