Onkyo TX-SR503 Service Manual page 71

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-11
Q201: CS494003CQZ (Multi-Standard Audio Decoder)-10/11
SD_BA, EXTRA19 --- SDRAM Bank Address Select, SRAM External Address Bus
SDRAM bank address select, SRAM external address bus 19. OUTPUT
SD_CS --- SDRAM Chip select
SDRAM chip select. OUTPUT
SD_RAS --- SDRAM Row Address Strobe
SDRAM row address strobe. OUTPUT
SD_CAS --- SDRAM Column Address Strobe
SDRAM column address strobe. OUTPUT
SD_WE --- SDRAM Write Enable
SDRAM write enable. OUTPUT
SD_DQM1 --- SDRAM Data Mask 1
SDRAM data mask 1. OUTPUT
SD_DQM0 --- SDRAM Data Mask 2
SDRAM data mask 0. OUTPUT
NV_CS, GPIO14 --- SRAM Chip Select, General Purpose I/O
SRAM/FLASH chip select. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT
NV_OE, GPIO15 --- SRAM Output Enable, General Purpose I/O
SRAM/FLASH output enable. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT
NV_WE, GPIO16 --- SRAM Write Enable, General Purpose I/O
SRAM/FLASH write enable. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT
UHS2, CS_OUT, GPIO17 --- Mode Select Bit 2, External Serial Memory Chip Select,
General Purpose I/O
DSPC control port mode select bit 2. This pin is sampled at the rising edge of RESET and is
one of three pins used to select the control port mode. In serial control port mode, this pin can
serve as an output to provide the chip-select for a serial EEPROM. This pin can act as a
general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT
TX-SR503/503E/8350