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A
B
8
7
FROM/TO LVDS
DBO9
DBO8
DBO7
DBO6
DBO5
DBO4
DBO3
DBO2
DGO9
DGO8
DGO7
6
DGO6
DGO5
DGO4
DGO3
DGO2
DRO9
DRO8
DRO7
DRO6
DRO5
DRO4
5
DRO3
DRO2
DHS
DVS
DENO
DVS1
DHS1
4
DBO2
DBO3
DBO4
DBO5
NR7501
4D03WGJ0470T5E
3
DBO6
DBO7
DBO8
DBO9
NR7502
4D03WGJ0470T5E
2
DENO
DVS1
DHS1
1
A
B
H-25
C
D
ADC2 SCHEMATIC DIAGRAM
3.3
3.3
3.3
3.3
0
3.3
3.3
3.3
3.3
1.8
3.3
0
0
0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
0
0
W871
3.3
SC_ADD_CTRL_IN
0
SC_ADD_CTRL_IN
0
98 SC_ADD_CTRL_IN
SC_ADD_CTRL_IN
W870
3.3
97 SC_ADD_CTRL_IN
TEST_MODE0
0
96 G_Y_OUT9
TEST_MODE1
W869
3.3
95 G_Y_OUT8
TEST_MODE2
0
TEST_MODE3
0
JG7501
TEST_OUT
C7502
3.3
VCC_BUF
0.1 B
C7505
1.8
VCC_CORE
0.1 B
0
PROCESS_CONTROL_IN
0
PROCESS_CONTROL_IN
3.3
CLK_VIDEO
0
VBLANK_IN
0
HBLANK_IN
0
JG7502
B_CB_CRCB_OUT0
0
JG7503
B_CB_CRCB_OUT1
0
VSS
C7503
1.8
VCC_CORE
0.1 B
3.3
B_CB_CRCB_OUT2
3.3
B_CB_CRCB_OUT3
3.3
B_CB_CRCB_OUT4
3.3
B_CB_CRCB_OUT5
128 VSS
0
VSS
127 B_CB_CRCB_OUT9
C7504
3.3
VCC_BUF
2 R_CR_IN1
0.1 B
3.3
B_CB_CRCB_OUT6
1 R_CR_IN0
3.3
B_CB_CRCB_OUT7
3.3
B_CB_CRCB_OUT8
3.3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
0 3.1 3.1 3.1
0 3.1 3.1 3.1 3.1 3.1
3.3
0
0
JG7508
JG7500
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
C
D
E
(SCALER PCB)
0
0
3.3
3.3
3.3
3.3
0
1.8
3.3
0
0
0
0
0
0
0
0
3.3
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
3.3
3.3
3.3
B_CB_CRCB_IN7
3.3
B_CB_CRCB_IN6
3.3
68 CLARITY_IN2
B_CB_CRCB_IN5
67 CLARITY_IN1
3.3
B_CB_CRCB_IN4
3.3
66 CLARITY_IN0
B_CB_CRCB_IN3
65 B_CB_CRCB_IN9
3.3
B_CB_CRCB_IN2
64 VCC_BUF
0
B_CB_CRCB_IN1
0
63 B_CB_CRCB_IN8
B_CB_CRCB_IN0
0
TEST_IN
1.8
VCC_CORE
0
VSS
3.3
SDA
3.3
SCL
VIDEO_ENHANCER
IC7501
3.3
CLK_SYSTEM
DV1000-75
0
OUTPUT_ENABLE_N_IN
3.3
VCC_BUF
0
VSS
3.3
R_CR_OUT9
3.3
R_CR_OUT8
3.3
R_CR_OUT7
3.3
R_CR_OUT6
0
VSS
34 R_CR_OUT1
3.3
R_CR_OUT5
3.3
33 R_CR_OUT0
R_CR_OUT4
32 G_Y_IN9
3.3
R_CR_OUT3
31 G_Y_IN8
3.3
R_CR_OUT2
1.8
VCC_CORE
3.3
VCC_BUF
0
0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0
0
3.4 3.3 3.3 3.3 1.8
0
0
3.3
3.3 3.3 3.3
0 3.3 3.3 3.3 3.3
JG7515
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
E
F
G
DB9
C7513
0.1 B
DB8
DB7
DB6
DB5
DB4
DB3
DB2
W872
JG7513
W973
JG7514
C7514
0.1 B
R7510
SDA1
R7509
100
SCL1
100
C7518
4
3
OSC
C7515
0.1 B
X7501
20MHz
0.1 B
1
2
NC
DRO9
DRO8
DRO7
DRO6
NR7505
4D03WGJ0470T5E
DRO5
DRO4
DRO3
DRO2
NR7506
C7512
4D03WGJ0470T5E
0.1 B
C7516
0.1 B
JG7511
JG7512
B7502
BLM18PG181SN1D
L7502
47uH
NLCV32T
PCBDS0
CEF156
F
G
H
8
7
FROM/TO MICON
DV1000_RESET
SDA1
SCL1
6
5
FROM/TO SCALER
DCLK2
DHS
DVS
DEN
DB9
DB8
DB7
DB6
DB5
4
DB4
DB3
DB2
DG9
DG8
DG7
DG6
DG5
DG4
DG3
DG2
3
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
FROM/TO REGULATOR
2
P.CON+1.8V
P.CON+3.3V
GND
1
H
H-26
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