Kenwood DVR-6100 Service Manual page 13

DVR-6100/6100K
3-11 Digital Audio Decoder : CS493263 (DSP B' D IC33)
Pin No. Pin Name
1,12,23 VDD(1~3)
2,13,24 VSS(1~3)
3 XMT958
4 WR,DS
5 RD,RW
6 A1, SCDIN
7 A0, SCCLK
8~11
DATA(7~0)
14~17
18 CS
19 SCDI0,SCDOUT
20 INTREQ ABOOT
21 EXTMEM
22 SDATAN
25 SCLKN
26 SLRCLKN
27 CMPDAT
28 CMPCLK
29 CMPREQ
30 CLKIN
31 CLKSEL
32 FLT2
33 FLT1
34 VDDA
35 VSSA
36 RESET
37 DD
38 DC
39 AUDAT2
40 AUDAT1
41 AUDAT0
42 LRCLK
43 SCLK
44 MCLK
4. Block Diagram of Shift Register : BU4094 (Front IC81)
2
DATA
CLOCK
3
1
STROBE
15
OUTPUT
ENABLE
(PARALLEL OUTPUT)
13
CIRCUIT DESCRIPTION
I/O
- Digital positive supplies.
- Digital ground.
0 SPDIF transmitter output (unused).
Host Write Strobe, Host Data Strobe, External Memory Write
I/O
Enable or General Purpose Input
Host Parallel Output Enable, Host parallel R/W, External
I/O
Memory Output Enable, General Purpose Input
1 Host address bit one or SPI serial control data input.
I Host parallel address bit zero or serial control pin clock.
I/O Data bus (7~0).
I Chip select input.
I/O Serial control data input and output.
I/O Control pin interrupt request, automatic boot enable.
I/O External memory chip select input/output.
I PCM audio data input.
I/O PCM audio input bit clock.
I/O PCM audio input sample rate clock.
I PCM audio data input.
I/O PCM audio input bit clock.
I/O PCM audio input sample rate clock.
I Master clock input.
I DSP clock select.
- Phase locked loop filter.
- Phase locked loop filter.
- Analog positive power supply for clock generator.
- Analog ground for clock generator PLL.
I Master reset input.
I/O This pin should be pulled up with an external 4.7kΩresistor.
I This pin should be pulled up with an external 4.7kΩresistor.
O Digital audio output 2.
O Digital audio output 1.
O Digital audio output 0.
I/O Audio output sample rate clock.
I/O Audio output bit clock.
I/O Audio master clock.
10
8-STAGE
SHIFT REGISTER
9
8-BIT
LATCHES
3-STATE
OUTPUTS
Q1 Q8
4~7, 11~14
Pin Description
Q's (SERIAL OUTPUT)
Qs (SERIAL OUTPUT)