Ine2 - Onkyo TX-SR502 Service Manual

IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-20
Q800: AK4588VQ (2/8-Channel Audio CODEC with DIR)-4
TERMINAL DESCRIPTION
No. Pin Name
55 AVDD
56 AVSS
57 RX0
58 NC
59 RX1
60 TEST1
61 RX2
62 NC
63 RX3
64 PVSS
65 R
66 PVDD
67 RX4
68 TEST2
69 RX5
70 CAD0
71 RX6
72 CAD1
73 RX7
74 I2C
75 DAUX2
76 VIN
77 MCLK
78 TX0
79 TX1
80 INT0
I/O Function
- Analog Power Supply Pin, 4.5V~5.5V
- Analog Ground Pin, 0V
Receiver Channel 0 Pin (Internal biased pin)
I
This channel is default in serial mode.
No Connect
-
This pin should be connected to PVSS.
I Receiver Channel 1 Pin (Internal biased pin)
Test 1 Pin
I
This pin should be connected to PVSS.
I Receiver Channel 2 Pin (Internal biased pin)
No Connect
-
This pin should be connected to PVSS.
I Receiver Channel 3 Pin (Internal biased pin)
- PLL Ground pin
External Resistor Pin
-
12k +/-1% resistor should be connected to PVSS externally.
- PLL Power supply pin, 5.0V
I Receiver Channel 4 Pin (Internal biased pin)
Test 2 Pin
I
This pin should be connected to PVSS.
I Receiver Channel 5 Pin (Internal biased pin)
I Chip Address 0 Pin (ADC/DAC part)
I Receiver Channel 6 Pin (Internal biased pin)
I Chip Address 1 Pin (ADC/DAC part)
I Receiver Channel 7 Pin (Internal biased pin)
Control Mode Select Pin.
I
"L": 4-wire Serial, "H": I
I Auxiliary Audio Data Input Pin (DIR/DIT part)
I V-bit Input Pin for Transmitter Output
I Master Clock Input Pin
O Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
When TX bit = "0", Transmit Channel (Through Data) Output 1 Pin.
O
When TX bit = "1", Transmit Channel (DAUX2 Data) Output Pin (Default).
O Interrupt 0 Pin
2
C Bus
TX-SR502/E/8250/HT-R520