Acer Aspire SA85 Service Manual page 40

DRAM Clock/Timing Control
Current CPU Frequency
Current DRAM Frequency 200 MHz
DRAM Timing Control
x DRAM CAS Latency
x RAS Active Time (tRAS)
x RAS Recharge Time (tRP) 3T
x RAS to CAS Delay (tRCD) 3T
: Move Enter: Select
F5: Previous Values
Parameter
Current CPU Frequency
Current DRAM Frequency
DRAM Timing Control
DRAM CAS Latency
RAS Active Time (tRAS)
RAS Precharge Time (tRP)
RAS to CAS Delay (tRCD)
34
Phoenix - AwardBIOS CMOS Setup Utilitye
DRAM Clock/Timing Control
133 MHz
[By SPD]
2.5T
6T
+/-/PU/PD: Value F10:Save
F7: Optimized Defaults
Detect the current CPU Frequency
Detect the current DRAM Frequency
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3.
The value is set at the factory depending on the DRAM installed. Do
not change the values in this field unless you change specifications of
the installed DRAM or the installed CPU.
This item controls the timing delay (in clock cycles) before the DRAM
starts a read command after receiving it.
This item allows you to set the amount of time a RAS can be kept
open for multiple accesses. High figures will improve performance.
This is the duration of the time interval during which the Row Address
Strobe signal to a DRAM is held low during normal Read and Write
Cycles. This is the munimum interval between completing one read
or write and starting another from the same (non-page mode) DRAM.
Techniques such as memory interleaving, or use of Page Mode
DRAM are often used to avoid this delay. Some chipsets require this
parameter in order to set up the memory configuration properly. The
RAS Precharge value is typically about the same as the RAM Access
(data read/write) time.
This is the amount of time a CAS is performed after a RAS. This
lower the better, but some DRAM does not support low figures.
Menu Level
ESC: Exit F1: General Help
Description
Item Help
Chapter 2