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IC BLOCK DIAGRAM & DESCRIPTION
IC103 M12L16161A-7TG (Synchronous DRAM)
Bank select
CLK
ADD
LCKE
LRAS
LCBR
CLK
CKE
PIN
CLK
System Clock
CS
Chip Enable
CKE
Clock Enable
A0~A10/AP
Address
BA
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input / Output Mask
IC104 LA6548NH-E (CD Driver)
PIN No. Pin Name
1
VCC1
Power supply (VCC2, short-circuit 28pin)
2
MUTE
Output ON/OFF terminal
3
VIN1
CH1, Input terminal
4
VG1
CH1, Input terminal(Gain setting)
5
VO1+
CH1, Output terminal(+)
6
VO1-
CH1, Output terminal(-)
7
(NC)
(Do not use)
8
(NC)
(Do not use)
9
VO2-
CH2, Output terminal(-)
10
VO2+
CH2, Output terminal(+)
11
VG2
CH2, Input terminal(Gain setting)
12
VIN2
CH2, Input terminal
13
REG_C
External PNP Connect to transistor collector
14
REG_B
External PNP Connect to transistor base
15
RESET
RESET output
Data Input Register
512K
512K
Column Decoder
Latency & Burst Length
Programming Register
LWE
LCAS
Timing Register
CS
RAS
CAS
WE L(U)DQM
NAME
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK,CKE
and L(U)DQM.
Makes system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Description (Function)
16
X
16
X
LDQM
LWCBR
Input Function
PIN No. Pin Name
16
CD
17
VIN3
18
VG3
19
VO3+
20
VO3-
21
(NC)
22
(NC)
23
VO4-
24
VO4+
25
VG4
26
VIN4
27
VREF
28
VCC2
- 10 -
LWE
1
V
DD
DQ0
2
LDQM
DQ1
3
V
4
SSQ
DQ2
5
DQ3
6
7
V
DDQ
DQi
DQ4
8
DQ5
9
10
V
SSQ
DQ6
11
DQ7
12
13
V
DDQ
LDQM
14
WE
15
CAS
16
RAS
17
CS
18
BA
19
A10/AP
20
A0
21
A1
22
A2
23
A3
24
V
25
DD
Description (Function)
RESET Connect to condenser
of dalay time setting
CH3, Input terminal(Gain setting)
CH3, Input terminal(Gain setting)
CH3, Output terminal(+)
CH3, Output terminal(-)
(Do not use)
(Do not use)
CH4, Output terminal(-)
CH4, Output terminal(+)
CH4, Input terminal(Gain setting)
CH4, Input terminal(Gain setting)
Standard applied voltage terminal
Power supply
(VCC1, short-circuit 1pin)
50
V
SS
DQ15
49
48
DQ14
47
V
SSQ
DQ13
46
DQ12
45
44
V
DDQ
43
DQ11
42
DQ10
41
V
SSQ
DQ9
40
DQ5
39
38
V
DDQ
37
N.C/RFU
36
UDQM
CLK
35
CKL
34
33
N.C
A9
32
31
A8
30
A7
29
A6
28
A5
27
A4
26
V
SS
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