MSI Z77A-G45 GAMING series User Manual page 60

BIOS Setup
▶ My OC Gene Intel C-State
Ths tem s used to enable/dsable the Intel C-State when OC Gene s started.
▶ My OC Gene Package C State lmt
Ths field allows you to specfic the C-state mode for OC Gene functon.
▶ My OC Gene Long duraton power lmt
Ths field allows you to customze Long duraton power lmt for OC Gene functon.
▶ My OC Gene Long duraton mantaned
Ths field allows you to customze Long duraton mantaned for OC Gene functon.
▶ My OC Gene Short duraton power lmt
Ths field allows you to customze Short duraton power mt for OC Gene functon.
▶ My CPU Core Voltage/ My OC Gene CPU I/O Voltage/ My OC Gene DRAM
Voltage/ My OC Gene GPU Voltage
These tems are used to specfic the voltage of CPU, Memory, GPU and chpset for
OC Gene functon.
▶ Current CPU Core Voltage/ Current CPU I/O Core Voltage/ Current DRAM Voltage/
Current GPU Voltage
These tems show current CPU/ CPU I/O/ DRAM/ GPU voltage. Read-only.
▶ DRAM Reference Clock
Ths tem allows you to specfic the DRAM Reference Clock for CPU. Please note the
overclockng behavor s not guaranteed.
▶ DRAM Frequency
Ths tem allows you to adjust the DRAM frequency. Please note the overclockng be-
havor s not guaranteed.
▶ Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
▶ DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect) EE-
PROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the followng
"Advanced DRAM Configuraton" sub-menu to be determned by BIOS based on the
configuratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to configure the
DRAM tmngs for each channel and the followng related "Advanced DRAM Configura-
ton" sub-menu manually.
▶ Advanced DRAM Configuraton
Press <Enter> to enter the sub-menu.
▶ Command Rate
Ths settng controls the DRAM command rate.
▶ tCL
Controls CAS latency whch determnes the tmng delay (n clock cycles) of startng
a read command after recevng data.
▶ tRCD
Determnes the tmng of the transton from RAS (row address strobe) to CAS (col-
umn address strobe). The less clock cycles, the faster the DRAM performance.
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